9.6.5. Scan chains 0, 1, 2, and 3

These scan chains allow serial access to the core logic, and to the EmbeddedICE macrocell for programming purposes. Each scan cell can perform two basic functions:

Scan chain 0

Purpose

Primarily for inter-device testing (EXTEST), and testing the ARM9TDMI core (INTEST). Scan chain 0 is selected using the SCAN_N instruction.

Length

184 bits.

INTEST allows serial testing of the core. The TAP controller must be placed in the INTEST mode after scan chain 0 has been selected:

  • During CAPTURE-DR, the current outputs from the core logic are captured in the output cells.

  • During SHIFT-DR, this captured data is shifted out while a new serial test pattern is scanned in, applying known stimuli to the inputs.

  • During RUN-TEST/IDLE, the core is clocked. Normally, the TAP controller only spends one cycle in RUN-TEST/IDLE. The whole operation can then be repeated.

EXTEST allows inter-device testing, useful for verifying the connections between devices in the design. The TAP controller must be placed in EXTEST mode after scan chain 0 has been selected:

  • During CAPTURE-DR, the current inputs to the core logic from the system are captured in the input cells.

  • During SHIFT-DR, this captured data is shifted out while a new serial test pattern is scanned in, applying known values on the core outputs.

  • During RUN-TEST/IDLE, the core is not clocked.

The operation can then be repeated.

The bit order of scan chain 0 is shown in Table 9.4.

Table 9.4. Scan chain 0 bit order

No.

Signal

Direction

1

ID[0]

Input

2

ID[1]

Input

3:31

ID[2:30]

Input

32

ID[31]

Input

33

SYSSPEED

Internal

34

WPTANDBKPT

Internal

35

DDEN

Output

36

DD[31]

Bidirectional

37

DD[30]

Bidirectional

38:66

DD[29:1]

Bidirectional

67

DD[0]

Bidirectional

68

DA[31]

Output

69

DA[30]

Output

70:98

DA[29:1]

Output

99

DA[0]

Output

100

IA[31]

Output

101

IA[30]

Output

102:129

IA[29:2]

Output

130

IA[1]

Output

131

IEBKPT

Input

132

DEWPT

Input

133

EDBGRQ

Input

134

EXTERN0

Input

135

EXTERN1

Input

136

COMMRX

Output

137

COMMTX

Output

138

DBGACK

Output

139

RANGEOUT0

Output

140

RANGEOUT1

Output

141

DBGRQI

Output

142

DDBE

Input

143

InMREQ

Output

144

DnMREQ

Output

145

DnRW

Output

146

DMAS[1]

Output

147

DMAS[0]

Output

148

PASS

Output

149

LATECANCEL

Output

150

ITBIT

Output

151

InTRANS

Output

152

DnTRANS

Output

153

nRESET

Input

154

nWAIT

Input

155

IABORT

Input

156

IABE

Input

157

DABORT

Input

158

DABE

Input

159

nFIQ

Input

160

nIRQ

Input

161

ISYNC

Input

162

BIGEND

Input

163

HIVECS

Input

164

CHSD[1]

Input

165

CHSD[0]

Input

166

CHSE[1]

Input

167

CHSE[0]

Input

168Reserved-

169

ISEQ

Output

170

InM[4]

Output

171

InM[3]

Output

172

InM[2]

Output

173

InM[1]

Output

174

InM[0]

Output

175

DnM[4]

Output

176

DnM[3]

Output

177

DnM[2]

Output

178

DnM[1]

Output

179

DnM[0]

Output

180

DSEQ

Output

181

DMORE

Output

182

DLOCK

Output

183

ECLK

Output

184

INSTREXEC

Output

Scan chain 1

Purpose

Primarily for debugging. Scan chain 1 is selected using the SCAN_N TAP controller instruction.

Length

67 bits.

The bit functions of scan chain 1 are shown in Table 9.5.

Table 9.5. Scan chain 1 bit function

Bit

Function

67:36

Data values DD[0:31]

35:33

Control bits DDEN, WPTANDBKPT, and SYSSPEED

32:1

Instruction data ID[31:0]

This scan chain is 67 bits long, 32 bits for data values, 32 bits for instruction data, and three control bits, SYSSPEED, WPTANDBKPT, and DDEN. The three control bits serve four different purposes:

  • Under normal INTEST test conditions, the DDEN signal can be captured and examined.

  • During EXTEST conditions, a known value can be scanned into DDEN to be driven into the rest of the system. If a logic 1 is scanned into DDEN, the data data bus DD[31:0] drives out the values stored in its scan cells. If a logic 0 is scanned into DDEN, DD[31:0] captures the current input values.

  • While debugging, the value placed in the SYSSPEED control bit determines whether the ARM922T synchronizes back to system speed before executing the instruction.

  • After the ARM922T has entered debug state, the first time SYSSPEED is captured and scanned out, its value tells the debugger whether the core has entered debug state due to a breakpoint (SYSSPEED LOW), or a watchpoint (SYSSPEED HIGH). You can have a watchpoint and breakpoint condition occur simultaneously. When a watchpoint condition occurs, the WPTANDBKPT bit must be examined by the debugger to determine whether the instruction currently in the execute stage of the pipeline is breakpointed. If so, WPTANDBKPT is HIGH, otherwise it is LOW.

Scan chain 2

Purpose

Allows access to the EmbeddedICE hardware registers. The order of the scan chain from TDI to TDO is:

  • read/write

  • register address bits 4 to 0

  • data values bits 31 to 0.

Length

38 bits.

Table 9.6 shows the bit functions of scan chain 2.

Table 9.6. Scan chain 2 bit function

Bit

Function

37

Read = 0

Write = 1

36:32

EmbeddedICE address register

31:0

Data values

To access this serial register, scan chain 2 must first be selected using the SCAN_N TAP controller instruction. The TAP controller must then be placed in INTEST mode:

  • No action is taken during CAPTURE-DR.

  • During SHIFT-DR, a data value is shifted into the serial register. Bits 32 to 36 specify the address of the EmbeddedICE hardware register to be accessed.

  • During UPDATE-DR, this register is either read or written depending on the value of bit 37 (0 = read).

Scan chain 3

Purpose

Allows the ARM922T to control an external boundary scan chain.

Length

User-defined.

Scan chain 3 is provided so that you can control an optional external boundary scan chain using the ARM922T. Typically this is used for a scan chain around the pad ring of a packaged device. The following control signals are provided, and are generated only when scan chain 3 is selected. These outputs are inactive at all other times:

DRIVEOUTBS

This switches the scan cells from system mode to test mode. This signal is asserted whenever the INTEST, EXTEST, CLAMP, or CLAMPZ instruction is selected.

PCLKBS

This is the update clock, generated in the UPDATE-DR state. Typically the value scanned into the chain is transferred to the cell output on the rising edge of this signal.

ICAPCLKBS, ECAPCLKBS

These are the capture clocks used to sample data into the scan cells during INTEST and EXTEST respectively. These clocks are generated in the CAPTURE-DR state.

SHCLK1BS, SHCLK2BS

These are non-overlapping clocks generated in the SHIFT-DR state that are used to clock the master and slave element of the scan cells respectively. When the state machine is not in the SHIFT-DR state, both these clocks are LOW.

nHIGHZ

You can use this signal to drive the outputs of the scan cells to the high impedance state. This signal is driven LOW when the HIGHZ instruction is loaded into the instruction register, and HIGH at all other times.

In addition to these control outputs, SDIN output and SDOUTBS input are also provided. When an external scan chain is in use, SDOUTBS must be connected to the serial data output and SDIN must be connected to the serial data input.

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