6.2. Unidirectional AMBA ASB interface

The AMBA Specification (REV 2.0) defines the Advanced Microcontroller Bus Architecture (AMBA) ASB interface for use with multiple masters. This requires that only the granted master controls and drives the bus system. The unidirectional AMBA ASB interface on the ARM922T supplies the constituent signals to make a bidirectional interface, that is input, output, and output enable. These signals are shown in Table 6.1.

Table 6.1. Relationship between bidirectional and unidirectional ASB interface

ASB signal

ARM922T input

ARM922T output

ARM922T output enable

AGNTxAGNT--
AREQx-AREQ-
BCLKBCLK--
BnRESBnRES--
DSELxDSEL--

BA[31:12]

-

AOUT[31:12]

ENBA

BA[11:2]

AIN[11:2]

AOUT[31:0]

ENBA

BA[1:0]

-

AOUT[1:0]

ENBA

BLOK

-

LOK

ENBA

BPROT[1:0]

-

PROT[1:0]

ENBA

BSIZE[1:0]

-

SIZE[1:0]

ENBA

BWRITE

WRITEIN

WRITEOUT

ENBA

BD[31:0]

DIN[31:0]

DOUT[31:0]

ENBD

BTRAN[1:0]

-

TRAN[1:0]

ENBTRAN

BERROR

ERRORIN

ERROROUT

ENSR

BLAST

LASTIN

LASTOUT

ENSR

BWAIT

WAITIN

WAITOUT

ENSR

An ASB bus cycle is defined from falling-edge to falling-edge transition of BCLK. The LOW part is referred to as phase 1, the HIGH part as phase 2. The timing is shown in Table 6.2, and is for reference only. It is assumed that the ARM922T macrocell is used in either an AMBA ASB or AMBA AHB system.

Table 6.2. ARM922T input/output timing

ARM922T inputTimingARM922T outputTiming
--AREQChange phase 2
AGNTSetup to rising BCLK--
DSELSetup to falling BCLK--
AIN[11:2] Setup to falling BCLKAOUT[31:0]Change phase 2
--LOKChange phase 2
--BPROT[1:0]Change phase 2
--SIZE[1:0]Change phase 2
WRITEINSetup to falling BCLKWRITEOUTChange phase 2
DIN[31:0]Setup to falling BCLKDOUT[31:0]Change phase 1
--TRAN[1:0]Change phase 2 (1)
ERRORINSetup to rising BCLKERROROUTFixed to 0
LASTINSetup to rising BCLKLASTOUTFixed to 0
WAITINSetup to rising BCLKWAITOUTChange phase 1

The timing for TRAN[1:0] is slightly different, so that if the ARM922T processor loses the GNT signal, TRAN[1:0] is changed to indicate A-TRAN in the same phase 1. Under these circumstances however, the ARM922T does not drive BTRAN[1:0] in the subsequent phase 2.

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