6.5. Level 2 cache support and performance analysis

The BURST[1:0] encoding, used with WRITEOUT and PROT[1:0], or BWRITE and BPROT[1:0], is intended to provide the information necessary to implement an efficient AHB wrapper. However, it also provides enough information for a level 2 cache to be implemented outside the ARM922T macrocell. Contact ARM for details. Encodings for the range of accesses supported by the ARM922T processor are listed in Table 6.8.

Table 6.8. ARM922T supported bus access types

BURST[1:0]WRITEOUTPROT[0]ARM922T bus access
00Read0Noncachable fetch
00Read1Noncachable LDR or LDM
00Write0-
00Write1Nonbuffered STR or STM
01Read0-
01Read1-
01Write0-
01Write1Write-back of 4 words
10Read0Instruction linefill of 8 words
10Read1Data linefill of 8 words
10Write0-
10Write1Write-back of 8 words
11Read0Instruction table walk
11Read1Data table walk
11Write0-
11Write1Buffered STR or STM

By monitoring the AMBA ASB bus transfers, qualified by the ARM922T AGNT and slave responses BERROR, BLAST, and BWAIT, you can implement a performance monitor outside the ARM922T macrocell. This might give the type of information shown in Example 6.1 after running a program. The performance monitor can be made accessible as a memory mapped peripheral or using JTAG on the ARM922T external scan chain.

Example 6.1. Typical output data from a performance monitor

I TLB Page Table Walks      : 1
D TLB Page Table Walks      : 1
4 Word Writebacks           : 10
8 Word Writebacks           : 5
I Cache Linefills           : 48
D Cache Linefills           : 28
NC Loads                    : 2
NC Fetches                  : 38
NCNB Stores                 : 2
NCB, WT or WB Miss Stores   : 13
BCLK Cycles                 : 1594
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