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The ARM9TDMI core has two clocks:
the memory clock GCLK
an internally TCK generated clock, DCLK.
During normal operation, the core is clocked by GCLK, and internal logic holds DCLK LOW. When the ARM922T is in the debug state, the core is clocked by DCLK under control of the TAP state machine, and GCLK can free run. The selected clock is output on the ECLK signal for use by the external system.
When the core is being debugged and is running from DCLK, nWAIT has no effect.
The two cases where the clocks switch are:
during debugging
during testing.
| Copyright © 2000, 2001 ARM Limited. All rights reserved. | ARM DDI 0184B |
| Non-Confidential | |
| PDF version | |
| Home > Debug Support > ARM922T core clocks |