11.5. PA TAG RAM test

PA TAG RAM test mode allows you to test reading and writing the memory array. The memory array comprises four segments out of a possible 128. Each segment comprises 64 lines. Each line is 26 bits wide. Before either a read or write can be executed, the segment and index locations must be written, defining the array entry. If this has been done, writing is achieved as a two-step process and reading as a one-step process.

  1. You must write a data pattern to a test location provided by the SSM.

  2. The data pattern is written into the RAM array and the index is incremented. Depending on the write location used the data pattern is either incremented or inverted. For a burst access, the second step is repeated.

There are five write locations and one read location. These are shown in Table 11.7.

Table 11.7. PA TAG RAM locations

Location

Address

Read/

write

Burst

Data

Index

0x04

Write

No

5:0

Segment

0x08

Write

No

6:0

Data pattern

0x0C

Write

No

25:0

RAM write, invert data pattern and increment index

0x10

Write

Yes

-

RAM write, increment data pattern and increment index

0x14

Write

Yes

-

RAM read and increment index

0x18

Read

Yes

31:6

When writing the data pattern, the write data is constructed as shown in Table 11.8.

Table 11.8. Construction of data pattern write data

Data pattern bits

Write data bits

25:21

28:24

20:14

22:16

13:7

14:8

6:0

6:0

For example:

Figure 11.2 shows the write data format.

Figure 11.2. Write data format

An example sequence to test lines 5 to 8 of memory segment 1 comprises:

  1. Enter PA TAG test mode.

  2. Write index = 5.

  3. Write segment = 1.

  4. Write data pattern = 0.

  5. Burst-4 RAM write and increment both data pattern and index.

  6. Write index = 5.

  7. Burst-4 RAM read and increment index.

  8. Exit test mode.

The TIF file equivalent of the above sequence is:

; PATAGRAM testmode
A 00000000
W 00000002
; load index counter 5
A 00000004
W 00000005
; load segment number 1
A 00000008
W 00000001
; load data pattern 0
A 0000000C
W 00000000
; ramwrite, increment data pattern and index, burst of 4
; 0x14 + 0x80 = 0x94
A 00000094
W 00000000
; ramwrite
W 00000000
; ramwrite
W 00000000
; ramwrite
W 00000000
; load index counter 5. Segment is unchanged at 1.
A 00000004
W 00000005
; ramread, increment index, burst of 4
; 0x18 + 0x80 = 0x98
A 00000098
R 00000000 FFFFFFC0
; ramread
R 00000040 FFFFFFC0
; ramread
R 00000080 FFFFFFC0
; ramread
R 000000C0 FFFFFFC0
A ZZZZZZZZ
; Exit Test Mode
A 00000000
W 00000000
; Exiting Test Mode
E ZZZZZZZZ.
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