9.1. About debug

Debug support is implemented using the ARM9TDMI CPU core embedded within the ARM922T. Throughout this chapter therefore, ARM9TDMI refers to this core.

The ARM922T debug interface is based on IEEE Std. 1149.1- 1990, Standard Test Access Port and Boundary-Scan Architecture. See this standard for an explanation of the terms used in this chapter and for a description of the TAP controller states.

The ARM922T contains hardware extensions for advanced debugging features. These are intended to ease the development of application software, operating systems, and the hardware itself.

The debug extensions allow the core to be stopped by one of the following:

When this happens, the ARM922T is said to be in debug state. At this point, you can examine the internal state of the core and the external state of the system. When examination is complete, you can restore the core and system state and resume program execution.

The ARM922T is forced into debug state either by a request on one of the external debug interface signals, or by an internal functional unit known as the EmbeddedICE macrocell. When in debug state, the core isolates itself from the memory system. You can then examine the core can while all other system activity continues as normal.

You can examine the internal state of the ARM922T using a JTAG-style serial interface. This allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, you can insert a store-multiple (STM) into the instruction pipeline to export the contents of the ARM9TDMI registers. This data can be serially shifted out without affecting the rest of the system.

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