9.9. Clock switching during test

Under serial test conditions, when test patterns are being applied to the core through the JTAG interface, the ARM9TDMI core must be clocked using DCLK. Entry into test is less automatic than debug and some care must be taken.

On the way into test, GCLK must be held LOW. You can now use the TAP controller to perform serial testing on the ARM9TDMI core. If scan chain 0 and INTEST are selected, DCLK is generated while the state machine is in RUN-TEST/IDLE state.

During EXTEST, DCLK is not generated.

On exit from test, you must select RESTART as the TAP controller instruction. When this is done, you can allow GCLK to resume. After INTEST testing, you must take care to ensure that the core is in a sensible state before switching back. The safest way to do this is either:

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