DRIVEOUTBS

Output

Boundary scan cell enable. This signal controls the multiplexors in the scan cells of an external boundary scan chain. This signal changes in the UPDATE-IR state when scan chain 3 is selected, and either the INTEST, EXTEST, CLAMP, or CLAMPZ instruction is loaded. If you do not connect an external boundary scan chain, you must leave this output unconnected.

ECAPCLKBS

Output

Extest capture clock for boundary scan. This is a TCK2 wide pulse generated when the TAP controller state machine is in the CAPTURE-DR state, the current instruction is EXTEST, and scan chain 3 is selected. This signal captures the chip-level inputs during EXTEST. If you do not connect an external boundary scan chain, you must leave this output unconnected.

ICAPCLKBS

Output

Intest capture clock. This is a TCK2 wide pulse generated when the TAP controller state machine is in the CAPTURE-DR state, the current instruction is INTEST, and scan chain 3 is selected. This signal captures the chip-level outputs during INTEST. If you do not connect an external boundary scan chain, you must leave this output unconnected.

IR[3:0]

Output

Tap controller instruction register. These four bits reflect the current instruction loaded into the TAP controller instruction register. The bits change on the falling edge of TCK when the state machine is in the UPDATE-IR state.

PCLKBS

Output

Boundary scan update clock. This is a TCK2 wide pulse generated when the TAP controller state machine is in the UPDATE-DR state, and scan chain 3 is selected. This signal is used by an external boundary scan chain as the update clock. If you do not connect an external boundary scan chain, you must leave this output unconnected.

RSTCLKBS

Output

Boundary scan reset clock. This signal denotes that either the TAP controller state machine is in the RESET state, or that nTRST has been asserted. You can use this to reset external boundary scan cells.

SCREG[4:0]

Output

Scan chain register. These five bits reflect the ID number of the scan chain currently selected by the TAP controller. These bits change on the falling edge of TCK when the TAP state machine is in the UPDATE-DR state.

SDIN

Output

Boundary scan serial input data. This signal contains the serial data to be applied to an external scan chain, and is valid around the falling edge of TCK.

SDOUTBS

Input

Boundary scan serial output data. This is the serial data out of the boundary scan chain (or other external scan chain). It must be set up to the rising edge of TCK. If you do not connect an external boundary scan chain, you must tie this input LOW.

SHCLK1BS

Output

Boundary scan shift clock phase 1. This control signal eases the connection of an external boundary scan chain. SHCLK1BS clocks the master half of the external scan cells. When in the SHIFT-DR state of the state machine and scan chain 3 is selected, SHCLK1BS follows TCK1. When not in the SHIFT-DR state, or when scan chain 3 is not selected, this clock is LOW. If you do not connect an external boundary scan chain, you must leave this output unconnected.

SHCLK2BS

Output

Boundary scan shift clock phase 2. This control signal eases the connection of an external boundary scan chain. SHCLK2BS clocks the slave half of the external scan cells. When in the SHIFT-DR state of the state machine and scan chain 3 is selected, SHCLK2BS follows TCK2. When not in the SHIFT-DR state, or when scan chain 3 is not selected, this clock is LOW. If you do not connect an external boundary scan chain, you must leave this output unconnected.

TAPID[31:0]

Input

This is the ARM922T device identification (ID) code test data register, accessible from the scan chains. You must tie this to an appropriate value when you instantiate the device:

31:28 Functionality revision

27:12 Product code

11:1 Manufacturer identity

0 IEEE specified = 1.

TAPSM[3:0]

Output

TAP controller state machine. This bus reflects the current state of the TAP controller state machine. These bits change off the rising edge of TCK.

TCK

Input

Test clock. The JTAG clock (the test clock).

TCK1

Output

TCK, phase 1. TCK1 is HIGH when TCK is HIGH, although there is a slight phase lag due to the internal clock non-overlap.

TCK2

Output

TCK, Phase 2. TCK2 is HIGH when TCK is LOW, although there is a slight phase lag due to the internal clock non-overlap.

TDI

Input

Test data input. JTAG serial input.

TDO

Output

Test data output. JTAG serial output.

nTDOEN

Output

Not TDO enable. When HIGH, this signal denotes that serial data is being driven out on the TDO output. nTDOEN is normally used as an output enable for a TDO pin in a packaged part.

TMS

Input

Test mode select. TMS selects the state that the TAP controller state machine must change to.

nTRST

Input

Not test reset. Active LOW reset signal for the boundary scan logic. This pin must be pulsed or driven LOW to achieve normal device operation, in addition to the normal device reset (BnRES).