ETMBIGEND

Output

The signal driving the ARM9TDMI BIGEND/BIGENDIAN input. When HIGH, the processor treats bytes in memory as big-endian format. When LOW, memory is treated as little-endian. This is a static configuration signal.

ETMCHSD[1:0]

Output

The coprocessor handshake decode bus driven into the ARM9TDMI core.

ETMCHSE[1:0]

Output

The coprocessor handshake execute bus driven into the ARM9TDMI core.

ETMCLOCK

Output

This clock times all operations in the ETM9. All outputs change from the rising edge and all inputs are sampled on the rising edge. The clock can be stretched in either phase.

ETMDA[31:0]

Output

The processor data MVA bus driven by the ARM9TDMI core.

ETMDABORT

Output

The Data Abort signal driven into the ARM9TDMI core. The DABORT signal is used to tell the processor that the requested data memory access is not allowed.

ETMDBGACK

Output

The debug acknowledge signal driven by the ARM9TDMI core. When HIGH this signal indicates that the ARM9TDMI core is in debug state.

ETMDD[31:0]

Output

The DD bus driven within the ARM922T processor.

ETMDMAS[1:0]

Output

The data memory access size bus driven by the ARM9TDMI core. These encode the size of a data memory access in the following cycle.

ETMDMORE

Output

The data control signal driven by the ARM9TDMI core. If HIGH at the end of the cycle then the data memory access is directly followed by a sequential data memory access.

ETMDnMREQ

Output

The data memory request signal driven by the ARM9TDMI core. If LOW at the end of a cycle then the processor requires a data memory access in the following cycle.

ETMDnRW

Output

The data read/write signal driven by the ARM9TDMI core. If LOW at the end of a cycle then any data memory access in the following cycle is a read. If HIGH, then it is a write.

ETMDSEQ

Output

The data sequential address signal driven by the ARM9TDMI core. If HIGH at the end of the cycle then any data memory access in the following cycle is sequential from the last data memory access.

ETMHIVECS

Output

The signal driving the ARM9TDMI HIVECS input. When LOW the ARM exception vectors start at address 0x0000 0000. When HIGH, the ARM exception vectors start at address 0xFFFF 0000. This is a static configuration signal.

ETMIA[31:1]

Output

The instruction MVA bus driven by the ARM9TDMI core.

ETMIABORT

Output

The instruction abort signal driven into the ARM9TDMI core.

ETMID15To8[15:8]

Output

A section from the ID input bus driven into the ARM9TDMI core.

ETMID31To24[31:24]

Output

A section from the ID input bus driven into the ARM9TDMI core.

ETMInMREQ

Output

The InMREQ signal driven by the ARM9TDMI core. If LOW at the end of the cycle then the processor requires an instruction memory access during the following cycle.

ETMINSTREXEC

Output

The INSTREXEC pipeline status signal driven by the ARM9TDMI core. The instruction executed signal indicates that the instruction in the Execute stage of the pipeline follower of the ETM9 has been executed.

ETMISEQ

Output

The ISEQ signal driven by the ARM9TDMI core. If HIGH at the end of the cycle then any instruction memory access during the following cycle is sequential from the last instruction memory access.

ETMITBIT

Output

The ITBIT signal driven by the ARM9TDMI core. When HIGH, denotes that the ARM is in Thumb state. When LOW, the processor is in ARM state. This signal is valid with the address.

ETMLATECANCEL

Output

The coprocessor late cancel signal driven by the ARM9TDMI core. If HIGH during the first memory cycle of a coprocessor instruction, then the coprocessor must cancel the instruction without changing any internal state. This signal is only asserted in cycles where the previous instruction accessed memory and a data abort occurred.

ETMPASS

Output

The PASS coprocessor signal driven by the ARM9TDMI core. This signal indicates that the instruction in the Execute stage of the pipeline follower of the ETM9 is executed.

ETMPWRDOWN

Input

When HIGH, indicates that the ETM9 can be powered down. The ARM922T processor uses this to stop the ETMCLOCK output. When this happens all other ETM<name> outputs are held stable.

ETMRNGOUT[1:0]

Output

The RANGEOUT[1:0] EmbeddedICE signals driven by the ARM. The EmbeddedICE RANGEOUT signals indicate that the corresponding watchpoint unit has matched the conditions currently present on the address, control and data buses. These signals are independent of the state of the enable control bit of the watchpoint unit.

ETMnWAIT

Output

You can stall the ETM9 by driving ETMnWAIT LOW. It must be held HIGH at all other times. ETMnWAIT is the nWAIT signal driven into the ARM9TDMI core.