The ITLB and DTLB are maintained using MCR and MRC instructions to CP15 registers 2, 3, 5, 6, 8, and 10, defined by the ARM v4T programmer’s model. Additional operations are available using MCR and MRC instructions to CP15 register 15. These operations are combined with those using registers 2, 3, 5, 6, 8, and 10 to enable testing of the TLBs entirely in software.

A modified subset of these MCR and MRC instructions are available in AMBA test for production test. See Chapter 11 AMBA Test Interface.

All MCR and MRC instructions to CP15 are available through the debug scan chains in CP15 Interpret Mode. This mode of access is intended to be used with a subset of the available CP15 MCR and MRC instructions, so that using other than the minimal subset causes unpredictable behavior. See Scan chains 4 and 15, the ARM922T memory system.

The register 2 operations are read and write. They are extended by the register 15 operations to allow individual control of the separate I and D Translation Table Base (TTB) registers, and are listed in Table B.9.

The register 3 operations are read and write. They are extended by the register 15 operations to allow individual control of the separate I and D Domain Access Control (DAC) registers, and are listed in Table B.10.

The register 5 operations are read and write, but the ability to access the I FSR is not architecturally defined in ARMv4T and is only intended for debug, when testing the TLB miss mechanism using aborts rather than hardware page table walks. Register 5 operations are listed in Table B.11. The register 15 operations are a duplication of the register 15 operations to the I FSR.

The register 6 operations are read and write. The I TLB is identical to the D TLB, but the I FAR is not architecturally defined, so the ability to access the I FAR is for testability only and the MCR and MRC instructions are described by the ARMv4T as being UNPREDICTABLE. Register 6 operations are listed in Table B.12.

The register 8 operations are all write-only. They are listed in Table B.13.

The register 10 operations are read and write. They are listed in Table B.14.

The register 15 operations that operate on the CAM, RAM1, and RAM2 are listed in Table B.15.

While the ARM922T memory system is a Harvard architecture, the TLBs are accessed using CData. This means the write operations can be combined to operate on both the I TLB and D TLB in parallel.

These register 15 operations are all issued as MCR, which means that the read and match operations have to be latched into the CP15.M.I or CP15.M.D in CP15. These are 32-bit registers that are read with the following CP15 MRC instruction:

Read from register CP15.M.<I or D>

Table B.16 summarizes C2, C3, C5, C6, C8, C10, and C15 operations.

Figure B.12 shows the format of Rd for CAM writes and data for CAM reads.

In Figure B.12, V is the Valid bit, P is the Preserve bit, and SIZE_C sets the memory region size. The allowed values of SIZE_C are shown in Table B.17.

Figure B.13 shows the format of Rd for RAM1 writes.

In Figure B.13, AP[3:0] determines the setting of the access permission bits for a memory region. The allowed values are listed in Table B.18.

Figure B.14 shows the data format for RAM1 reads.

In Figure B.14, bits [24:22] are only valid for a match operation. In this case the values listed in Table B.19 apply.

Figure B.15 shows the Rd format for RAM2 writes, and the data format for RAM2 reads.

In Figure B.15, SIZE_R2 sets the memory region size. The allowed values of SIZE_R2 are shown in Table B.20.