The AMBA bus interface of the ARM922T conforms to the AMBA Specification (Rev 2.0). See this document for the relevant timing diagrams.

Figure 13.1 shows the signal parameters for the FCLK timed coprocessor interface.

Figure 13.2 shows the signal parameters for the BCLK timed coprocessor interface.

Figure 13.3 shows the ARM922T FCLK related signal timing.

Figure 13.4 shows the ARM922T BCLK related signal timing.

Figure 13.5 shows the SDOUTBS to TDO signal relationship.

Figure 13.6 shows the relationship between nTRST and the following signals:

Figure 13.7 shows the JTAG output signal timing parameters.

Figure 13.8 shows the JTAG input signal timing parameters.

Figure 13.9 shows the FCLK related debug output timing parameters.

Figure 13.10 shows the BCLK related debug output timing parameters.

Figure 13.11 shows the TCK related debug output timing parameters.

Figure 13.12 shows the EDBGRQ to DBGRQI relationship.

Figure 13.13 shows the DBGEN to output relationship.

Figure 13.14 shows the BCLK related Trace Interface Port timing parameters.

Figure 13.15 shows the FCLK related Trace Interface Port timing parameters.

Figure 13.16 shows the BnRES timing.

You can assert BnRES LOW asynchronously during either BCLK phase, but you must de-assert it during the BCLK LOW phase. You must keep BnRES asserted for a minimum of five BCLK cycles to ensure a complete reset of the ARM922T.

Figure 13.17 shows the ARM922T ASB slave transfer timing parameters.

Figure 13.18 and Figure 13.19 show the ARM922T ASB master transfer timing parameters.