13.3. Timing definitions for the ARM922T Trace Interface Port

Table 13.2 shows the timing parameters of signals used with the ARM922T Trace Interface Port.

Table 13.2. ARM922T Trace Interface Port timing definitions

Timing parameter

Description

No arcs for ETMPWRDOWN

-

Tbetmbigendd

ETMBIGEND output delay from BCLK rising

Tbetmbigendh

ETMBIGEND output hold from BCLK rising

Tbetmchsdd

ETMCHSD[1:0] output delay from BCLK rising

Tbetmchsdh

ETMCHSD[1:0] hold from BCLK rising

Tbetmchsed

ETMCHSE[1:0] output delay from BCLK rising

Tbetmchseh

ETMCHSE[1:0] hold from BCLK rising

Tbetmckf

ETMCLOCK falling output delay from BCLK falling

Tbetmckr

ETMCLOCK rising output delay from BCLK rising

Tbetmdabortd

ETMDABORT output delay from BCLK rising

Tbetmdaborth

ETMDABORT output hold from BCLK rising

Tbetmdad

ETMDA[31:0] output delay from BCLK rising

Tbetmdah

ETMDA[31:0] output hold from BCLK rising

Tbetmdbgackd

ETMDBGACK output delay from BCLK rising

Tbetmdbgackh

ETMDBGACK output hold from BCLK rising

Tbetmddd

ETMDD[31:0] output delay from BCLK rising

Tbetmddh

ETMDD[31:0] output hold from BCLK rising

Tbetmdmasd

ETMDMAS[1:0] output delay from BCLK rising

Tbetmdmash

ETMDMAS[1:0] output hold from BCLK rising

Tbetmdmored

ETMDMORE output delay from BCLK rising

Tbetmdmoreh

ETMDMORE output hold from BCLK rising

Tbetmdnmreqd

ETMDnMREQ output delay from BCLK rising

Tbetmdnmreqh

ETMDnMREQ output hold from BCLK rising

Tbetmdnrwd

ETMDnRW output delay from BCLK rising

Tbetmdnrwh

ETMDnRW output hold from BCLK rising

Tbetmdseqd

ETMDSEQ output delay from BCLK rising

Tbetmdseqh

ETMDSEQ output hold from BCLK rising

Tbetmhivecsd

ETMHIVECS output delay from BCLK rising

Tbetmhivecsh

ETMHIVECS output hold from BCLK rising

Tbetmiabortd

ETMIABORT output delay from BCLK rising

Tbetmiaborth

ETMIABORT output hold from BCLK rising

Tbetmiad

ETMIA[31:1] output delay from BCLK rising

Tbetmiah

ETMIA[31:1] output hold from BCLK rising

Tbetmid15to8d

ETMID15TO8[15:8] output delay from BCLK rising

Tbetmid15to8h

ETMID15TO8[15:8] output hold from BCLK rising

Tbetmid31to24d

ETMID31TO24[31:24] output delay from BCLK rising

Tbetmid31to24h

ETMID31TO24[31:24] output hold from BCLK rising

Tbetminmreqd

ETMInMREQ output delay from BCLK rising

Tbetminmreqh

ETMInMREQ output hold from BCLK rising

Tbetminstrexecd

ETMINSTREXEC output delay from BCLK rising

Tbetminstrexech

ETMINSTREXEC output hold from BCLK rising

Tbetmiseqd

ETMISEQ output delay from BCLK rising

Tbetmiseqh

ETMISEQ output hold from BCLK rising

Tbetmitbitd

ETMITBIT output delay from BCLK rising

Tbetmitbith

ETMITBIT output hold from BCLK rising

Tbetmlatecanceld

ETMLATECANCEL output delay from BCLK rising

Tbetmlatecancelh

ETMLATECANCEL output hold from BCLK rising

Tbetmnwaitd

ETMnWAIT output delay from BCLK rising

Tbetmnwaith

ETMnWAIT output hold from BCLK rising

Tbetmpassd

ETMPASS output delay from BCLK rising

Tbetmpassh

ETMPASS output hold from BCLK rising

Tbetmrngoutd

ETMRNGOUT[1:0] output delay from BCLK rising

Tbetmrngouth

ETMRNGOUT[1:0] hold from BCLK rising

Tfetmbigendd

ETMBIGEND output delay from FCLK rising

Tfetmbigendh

ETMBIGEND output hold from FCLK rising

Tfetmchsdd

ETMCHSD[1:0] output delay from FCLK rising

Tfetmchsdh

ETMCHSD[1:0] output hold from FCLK rising

Tfetmchsed

ETMCHSE[1:0] output delay from FCLK rising

Tfetmchseh

ETMCHSE[1:0] output hold from FCLK rising

Tfetmckf

FETMCLOCK falling output delay from FCLK falling

Tfetmckr

FETMCLOCK rising output delay from FCLK rising

Tfetmdabortd

ETMDABORT output delay from FCLK rising

Tfetmdaborth

ETMDABORT output hold from FCLK rising

Tfetmdad

ETMDA[31:0] output delay from FCLK rising

Tfetmdah

ETMDA[31:0] output hold from FCLK rising

Tfetmdbgackd

ETMDBGACK output delay from FCLK rising

Tfetmdbgackh

ETMDBGACK output hold from FCLK rising

Tfetmddd

ETMDD[31:0] output delay from FCLK rising

Tfetmddh

ETMDD[31:0] output hold from FCLK rising

Tfetmdmasd

ETMDMAS[1:0] output delay from FCLK rising

Tfetmdmash

ETMDMAS[1:0] output hold from FCLK rising

Tfetmdmored

ETMDMORE output delay from FCLK rising

Tfetmdmoreh

ETMDMORE output hold from FCLK rising

Tfetmdnmreqd

ETMDnMREQ output delay from FCLK rising

Tfetmdnmreqh

ETMDnMREQ output hold from FCLK rising

Tfetmdnrwd

ETMDnRW output delay from FCLK rising

Tfetmdnrwh

ETMDnRW output hold from FCLK rising

Tfetmdseqd

ETMDSEQ output delay from FCLK rising

Tfetmdseqh

ETMDSEQ output hold from FCLK rising

Tfetmhivecsd

ETMHIVECS output delay from FCLK rising

Tfetmhivecsh

ETMHIVECS output hold from FCLK rising

Tfetmiabortd

ETMIABORT output delay from FCLK rising

Tfetmiaborth

ETMIABORT output hold from FCLK rising

Tfetmiad

ETMIA[31:1] output delay from FCLK rising

Tfetmiah

ETMIA[31:1] output hold from FCLK rising

Tfetmid15to8d

ETMID15TO8[15:8] output delay from FCLK rising

Tfetmid15to8h

ETMID15TO8[15:8] output hold from FCLK rising

Tfetmid31to24d

ETMID31TO24[31:24] output delay from FCLK rising

Tfetmid31to24h

ETMID31TO24[31:24] output hold from FCLK rising

Tfetminmreqd

ETMInMREQ output delay from FCLK rising

Tfetminmreqh

ETMInMREQ output hold from FCLK rising

Tfetminstrexecd

ETMINSTREXEC output delay from FCLK rising

Tfetminstrexech

ETMINSTREXEC output hold from FCLK rising

Tfetmiseqd

ETMISEQ output delay from FCLK rising

Tfetmiseqh

ETMISEQ output hold from FCLK rising

Tfetmitbitd

ETMITBIT output delay from FCLK rising

Tfetmitbith

ETMITBIT output hold from FCLK rising

Tfetmlatecanceld

ETMLATECANCEL output delay from FCLK rising

Tfetmlatecancelh

ETMLATECANCEL output hold from FCLK rising

Tfetmnwaitd

ETMnWAIT output delay from FCLK rising

Tfetmnwaith

ETMnWAIT output hold from FCLK rising

Tfetmpassd

ETMPASS output delay from FCLK rising

Tfetmpassh

ETMPASS output hold from FCLK rising

Tfetmrngoutd

ETMRNGOUT[1:0] output delay from FCLK rising

Tfetmrngouth

ETMRNGOUT[1:0] output hold from FCLK rising

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