13.2. ARM922T timing parameters

Table 13.1 shows the ARM922T timing parameters.

Table 13.1. ARM922T timing parameters

Timing parameter

Description

No arcs for CPEN [1]

No arcs for ERROROUT [2]

No arcs for ISYNC a

No arcs for LASTOUT b

No arcs for TRACK a

No arcs for VINITHI a

Tbbigd

BIGENDOUT output delay from BCLK falling

Tbbigh

BIGENDOUT output hold from BCLK falling

Tbcand

CPLATECANCEL output delay from BCLK falling

Tbcanh

CPLATECANCEL output hold from BCLK falling

Tbcdnh

CPDIN[31:0] input hold from BCLK falling

Tbcdns

CPDIN[31:0] input setup to BCLK falling

Tbchsdh

CHSDE[1:0] input hold from BCLK falling

Tbchsds

CHSDE[1:0] input setup to BCLK falling

Tbchseh

CHSEX[1:0] input hold from BCLK falling

Tbchses

CHSEX[1:0] input setup to BCLK falling

Tbcomd

COMMTX/COMMRX output delay from BCLK rising

Tbcomh

COMMTX/COMMRX output hold from BCLK rising

Tbcpdoutd

CPDOUT[31:0] output delay from BCLK falling

Tbcpdouth

CPDOUT[31:0] output hold from BCLK falling

Tbcpidd

CPID[31:0] output delay from BCLK falling

Tbcpidh

CPID[31:0] output hold from BCLK falling

Tbcpkf

CPCLK falling output delay from BCLK falling

Tbcpkr

CPCLK rising output delay from BCLK rising

Tbcpmreqd

nCPMREQ output delay from BCLK falling.

Tbcpmreqh

nCPMREQ output hold from BCLK falling

Tbcptbitd

CPTBIT output delay from BCLK falling.

Tbcptbith

CPTBIT output hold from BCLK falling

Tbdbqh

EDBGRQ input hold from BCLK falling

Tbdbqs

EDBGRQ input setup to BCLK falling

Tbdckd

DBGACK output delay from BCLK rising

Tbdckh

DBGACK output hold from BCLK rising

Tbdwph

DEWPT input hold from BCLK rising [3]

Tbdwps

DEWPT input setup to BCLK rising c

Tbekf

ECLK falling output delay from BCLK falling

Tbekr

ECLK rising output delay from BCLK rising

Tbexth

EXTERN0/EXTERN1 input hold from BCLK falling

Tbexts

EXTERN0/EXTERN1 input setup to BCLK falling

Tbibkh

IEBKPT hold after BCLK rising c

Tbibks

IEBKPT input setup to BCLK rising c

Tbinth

nFIQ/nIRQ input hold from BCLK falling

Tbints

nFIQ/nIRQ input setup to BCLK falling

Tbinxd

INSTREXEC output delay from BCLK falling c

Tbinxh

INSTREXEC output hold from BCLK falling c

Tbnwtd

nCPWAIT output delay from BCLK rising

Tbnwth

nCPWAIT output hold from BCLK rising

Tbpasd

CPPASS output delay from BCLK rising

Tbpash

CPPASS output hold from BCLK rising

Tbrg0d

RANGEOUT0 output delay from BCLK falling

Tbrg0h

RANGEOUT0 output hold from BCLK falling

Tbrg1d

RANGEOUT1 output delay from BCLK falling

Tbrg1h

RANGEOUT1 output hold from BCLK falling

Tbrst

COMMRX/COMMTX/DBGACK/DBGRQI/DRIVEOUTBS/ IR[3:0]/RANGEOUT0/RANGEOUT1/RSTCLKBS/ SCREG[3:0]/SDIN/ TAPSM[3:0]/TDO/nTDOEN output delay from nTRST falling

Tbrtd

RSTCLKBS output delay from TCK

Tbrth

RSTCLKBS hold time from TCK

TbtransdnCPTRANS output delay from BCLK falling
TbtranshnCPTRANS output hold from BCLK falling

Tcapf

ECAPCLKBS/ICAPCLKBS/PCLKBS falling output delay from TCK rising

Tcapr

ECAPCLKBS/ICAPCLKBS/PCLKBS rising output delay from TCK rising

Tclkh

BCLK minimum width HIGH phase

Tclkl

BCLK minimum width LOW phase

Tclktsth

BCLK minimum width HIGH phase in AMBA test mode

Tclktstl

BCLK minimum width LOW phase in AMBA test mode

Tdebugd

COMMRX/COMMTX/DBGACK/DBGRQI/RANGEOUT0/ RANGEOUT1 output delay from TCK when in debug state c

Tdebugh

COMMRX/COMMTX/DBGACK/DBGRQI/RANGEOUT0/ RANGEOUT1 output hold from TCK when in debug state c

Tdgid

DBGRQI output delay from TCK falling

Tdgih

DBGRQI output hold from TCK falling

Tdih

TDI/TMS input hold from TCK rising

Tdis

TDI/TMS input setup to TCK rising

Tdrbsd

DRIVEOUTBS output delay from TCK falling c

Tdrbsh

DRIVEOUTBS output hold from TCK falling c

Tedqd

DBGRQI output delay from EDBGRQ rising or falling

Tedqh

DBGRQI output hold from EDBGRQ rising or falling

Tfbigd

BIGENDOUT output delay from FCLK falling

Tfbigh

BIGENDOUT output hold from FCLK falling

Tfcand

CPLATECANCEL output delay from FCLK falling

Tfcanh

CPLATECANCEL output hold from FCLK falling

Tfcdnh

CPDIN[31:0] input hold from FCLK falling

Tfcdns

CPDIN[31:0] input setup to FCLK falling

Tfchsdh

CHSDE[1:0] input hold to FCLK falling

Tfchsds

CHSDE[1:0] input setup to FCLK falling

Tfchseh

CHSEX[1:0] input hold to FCLK falling

Tfchses

CHSEX[1:0] input setup to FCLK falling

Tfclkh

FCLK minimum width HIGH phase

Tfclkl

FCLK minimum width LOW phase

Tfcomd

COMMTX/RX output delay from FCLK rising

Tfcomh

COMMTX/RX output hold from FCLK rising

Tfcpdoutd

CPOUT[31:0] output delay from FCLK falling

Tfcpdouth

CPOUT[31:0] output hold from FCLK falling

Tfcpidd

CPID[31:0] output delay from FCLK falling

Tfcpidh

CPID[31:0] output hold from FCLK falling

Tfcpkf

CPCLK falling output delay from FCLK falling

Tfcpkr

CPCLK rising output delay from FCLK rising

Tfcpmreqd

nCPMREQ output delay from FCLK falling

Tfcpmreqh

nCPMREQ output hold time from FCLK falling

Tfcptbitd

CPTBIT output delay from FCLK falling

Tfcptbith

CPTBIT output hold time from FCLK falling

Tfdbqh

EDBGRQ input hold from FCLK falling

Tfdbqs

EDBGRQ input setup to FCLK falling

Tfdckd

DBGACK output delay from FCLK rising

Tfdckh

DBGACK output hold from FCLK rising

Tfdwph

DEWPT input hold from FCLK rising c

Tfdwps

DEWPT input setup to FCLK rising c

Tfekf

ECLK falling output delay from FCLK falling

Tfekr

ECLK rising output delay from FCLK rising

Tfexth

EXTERN0/1 output hold after FCLK falling

Tfexts

EXTERN0/1 input setup to FCLK falling

Tffkf

FCLKOUT falling output delay from FCLK falling

Tffkr

FCLKOUT rising output delay from FCLK rising

Tfibkh

IEBKPT input hold from FCLK rising c

Tfibks

IEBKPT input setup to FCLK rising c

Tfinth

nFIQ/nIRQ input hold from FCLK falling

Tfints

nFIQ/nIRQ input setup to FCLK falling

Tfinxd

INSTREXEC output delay from FCLK falling c

Tfinxh

INSTREXEC output hold from FCLK falling c

Tfnwtd

nCPWAIT output delay from FCLK rising

Tfnwth

nCPWAIT output hold from FCLK rising

Tfpasd

CPPASS output delay from FCLK rising

Tfpash

CPPASS output hold from FCLK rising

Tfrg0d

RANGEOUT0 output delay from FCLK falling

Tfrg0h

RANGEOUT0 output hold from FCLK falling

Tfrg1d

RANGEOUT1 output delay from FCLK falling

Tfrg1h

RANGEOUT1 output hold from FCLK falling

Tftransd

nCPTRANS output delay from FCLK falling

Tftransh

nCPTRANS output hold time from FCLK falling

Tiha

AIN[11:2] input hold from BCLK rising

Tihagnt

AGNT input hold from BCLK falling

Tihd

DIN[31:0] input hold from BCLK falling

Tihdsel

DSEL input hold from BCLK rising

Tiherr

ERRORIN input hold from BCLK rising

Tihlast

LASTIN input hold from BCLK rising

Tihnres

BnRES input rising hold from BCLK falling

Tihwait

WAITIN input hold from BCLK rising

Tihwr

WRITEIN input hold from BCLK rising

Tirsd

IREG[3:0]/SCREG[3:0] output delay from TCK falling

Tirsh

IREG[3:0]/SCREG[3:0] output hold from TCK falling

Tisa

AIN[11:2] input setup to BCLK falling

Tisagnt

AGNT input setup to BCLK rising

Tisd

DIN[31:0] input setup to BCLK falling

Tisdsel

DSEL input setup to BCLK falling

Tiserr

ERRORIN input setup to BCLK rising

Tislast

LASTIN input setup to BCLK rising

Tisnres

BnRES input rising setup to BCLK rising

Tiswait

WAITIN input setup to BCLK rising

Tiswr

WRITEIN input setup to BCLK rising

Tncmahbd

NCMAHB output delay from BCLK rising

Tncmahbh

NCMAHB output hold from BCLK rising

Toha

AOUT[31:0] output hold from BCLK rising

Tohareq

AREQ output hold from BCLK rising

Tohastb

ASTB output hold from BCLK rising

Tohbst

BURST[1:0] output hold from BCLK rising

Tohd

DOUT[31:0] output hold from BCLK falling

Tohenba

ENBA output hold from BCLK rising or falling

Tohenbd

ENBD output hold from BCLK falling

Tohensr

ENSR output hold from BCLK rising or falling

Tohentr

ENBTRAN output hold from BCLK rising or falling

Tohlok

LOK output hold from BCLK rising

Tohprot

PROT[1:0] output hold from BCLK rising

Tohsize

SIZE[1:0] output hold from BCLK rising

Tohtr

TRAN[1:0] output hold from BCLK rising

Tohwait

WAITOUT output hold from BCLK falling

Tohwrite

WRITEOUT output hold from BCLK rising

Tova

AOUT[31:0] output delay from BCLK rising

Tovareq

AREQ output delay from BCLK rising

Tovastb

ASTB output delay from BCLK rising

Tovbst

BURST[1:0] output delay from BCLK rising

Tovd

DOUT[31:0] output delay from BCLK falling

Tovenba

ENBA output delay from BCLK rising or falling

Tovenbd

ENBD output delay from BCLK falling

Tovensr

ENSR output delay from BCLK rising or falling

Toventr

ENBTRAN output delay from BCLK rising or falling

Tovlok

LOK output delay from BCLK rising

Tovprot

PROT[1:0] output delay from BCLK rising

Tovsize

SIZE[1:0] output delay from BCLK rising

Tovtr

TRAN[1:0] output delay from BCLK rising

Tovtra

TRAN[1:0] output delay from AGNT rising or falling

Tovwait

WAITOUT output delay from BCLK falling

Tovwrite

WRITEOUT output delay from BCLK rising

Trgen

RANGEOUT0/RANGEOUT1 falling output delay from DBGEN falling

Tsdnd

SDIN output delay from TCK falling

Tsdnh

SDIN output hold from TCK falling

Tshkf

SHCLK1BS falling output delay from TCK falling d

Tshkf

SHCLK2BS falling output delay from TCK rising d

Tshkr

SHCLK1BS rising output delay from TCK rising [4]

Tshkr

SHCLK2BS rising output delay from TCK falling d

Ttckf

TCK1 falling output delay from TCK falling [5]

Ttckf

TCK2 falling output delay from TCK rising e

Ttckh

TCK minimum width HIGH phase

Ttckl

TCK minimum width LOW phase

Ttckr

TCK1 rising output delay from TCK rising e

Ttckr

TCK2 rising output delay from TCK falling e

Ttdod

TDO output delay from TCK falling

Ttdoh

TDO output hold from TCK falling

Ttdsd

TDO output delay from SDOUTBS rising or falling

Ttdsh

TDO output hold from SDOUTBS rising or falling

Ttekf

ECLK falling output delay from TCK falling

Ttekr

ECLK rising output delay from TCK rising

Tticd

COMMRX/COMMTX/DBGACK/DBGRQI/DRIVEOUTBS/ ECAPCLKBS/ECLK/FCLKOUT/ICAPCLKBS/IR[3:0]/ RANGEOUT0/RANGEOUT1/RSTCLKBS/SCREG[3:0]/SDIN/ SHCLK1BS/SHCLK2BS/TAPSM[3:0]/TCK1/TCK2/TDO/ nTDOEN generic output delay from BCLK during AMBA test c

Ttich

COMMRX/COMMTX/DBGACK/DBGRQI/DRIVEOUTBS/ ECAPCLKBS/ECLK/FCLKOUT/ICAPCLKBS/IR[3:0]/ RANGEOUT0/RANGEOUT1/RSTCLKBS/SCREG[3:0]/SDIN/ SHCLK1BS/SHCLK2BS/TAPSM[3:0]/TCK1/TCK2/TDO/ nTDOEN generic output hold from BCLK during AMBA test c

Ttoed

nTDOEN output delay from TCK falling

Ttoeh

nTDOEN output hold from TCK falling

Ttpmd

TAPSM[3:0] output delay from TCK falling

Ttpmh

TAPSM[3:0] output hold from TCK falling

Tzero

BnRES falling setup to BCLK falling [6]

Tzero

BnRES falling hold from BCLK falling f

  

[1] It is assumed that this signal is static.

[2] Permanently driven to 0.

[3] This timing parameter is not shown in any diagram in this chapter.

[4] Tshkr is greater than Tshkf to ensure non-overlapping SHCLK1BS and SHCLK2BS.

[5] Ttckr is greater than Ttckf to ensure non-overlapping TCK1 and TCK2.

[6] This parameter is always zero because the timing arcs refer to asynchronous assertion.

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