3.2. MMU program accessible registers

Table 3.1 lists the CP15 registers that are used in conjunction with page table descriptors stored in memory to determine the operation of the MMU.

Table 3.1. CP15 register functions




Register description

Control register


M, A, S, R

Contains bits to enable the MMU (M bit), enable data address alignment checks (A bit), and to control the access protection scheme (S bit and R bit).

Translation table base register



Holds the physical address of the base of the translation table maintained in main memory. This base address must be on a 16KB boundary and is common to both TLBs.

Domain access control register



Comprises 16 2-bit fields. Each field defines the access control attributes for one of 16 domains (D15–D0).

Fault status register

5 (I and D)


Indicates the cause of a Data or Prefetch Abort, and the domain number of the aborted access, when an abort occurs. Bits 7:4 specify which of the 16 domains (D15–D0) was being accessed when a fault occurred. Bits 3:0 indicate the type of access being attempted. The value of all other bits is unpredictable. The encoding of these bits is shown in Table 3.9.

Fault address register

6 (D)


Holds the MVA associated with the access that caused the Data Abort. See Table 3.9 for details of the address stored for each type of fault.

You can use ARM9TDMI register 14 to determine the VA associated with a Prefetch Abort.

TLB operations register



You can write to this register to make the MMU perform TLB maintenance operations. These are either invalidating all the (unpreserved) entries in the TLB, or invalidating a specific entry.

TLB lockdown register

10 (I and D)

31:20 and 0

Allows specific page table entries to be locked into the TLB and the TLB victim index to be read or written:

  • opcode 2 = 0x0 accesses the D TLB lockdown register

  • opcode 2 = 0x1 accesses the I TLB lockdown register.

Locking entries in the TLB guarantees that accesses to the locked page or section can proceed without incurring the time penalty of a TLB miss. This allows the execution latency for time-critical pieces of code such as interrupt handlers to be minimized.

All the CP15 MMU registers, except register 8, contain state. You can read them using MRC instructions, and write them using MCR instructions. Registers 5 and 6 are also written by the MMU during a Data Abort. Writing to Register 8 causes the MMU to perform a TLB operation, to manipulate TLB entries. This register cannot be read. The Instruction TLB (I TLB) and Data TLB (D TLB) both have a copy of register 10. The opcode_2 field in the CP15 instruction is used to determine the one accessed.

CP15 is described in Chapter 2 Programmer’s Model, with details of register formats and the coprocessor instructions you can use to access them.

Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DDI 0184B