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| Home > Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM > DCache and write buffer > DCache lockdown | |||
You can lock data into the DCache, causing the DCache to guarantee a hit, and provide optimum and predictable execution time. If you enable the DCache, a DCache lookup is performed for each load. If the DCache misses and the Ctt=1 then an eight-word linefill is performed. The entry to be replaced is selected by the victim pointer. You can lock data into the DCache by controlling the victim pointer, and forcing loads to the DCache. You lock data in the DCache by first ensuring the data to be locked is not already in the cache. You can ensure this by cleaning and invalidating either the whole DCache or specific lines. Example 4.2 shows DCache invalidate and clean operations that you can perform to do this.
Example 4.2. DCache invalidate and clean operations
MCR p15, 0, Rd, c7, c6, 0 ; Invalidate DCache
MCR p15, 0, Rd, c7, c6, 1 ; Invalidate DCache single entry using MVA
MCR p15, 0, Rd, c7, c10, 1 ; Clean DCache single entry using MVA
MCR p15, 0, Rd, c7, c14, 1 ; Clean and Invalidate DCache single entry using MVA
MCR p15, 0, Rd, c7, c10, 2 ; Clean DCache single entry using Index
MCR p15, 0, Rd, c7, c14, 2 ; Clean and Invalidate DCache single entry using Index
You can then use a short software routine to load the data
into the DCache. You can locate the software routine in a cachable
region of memory providing it does not contain any loads or stores.
You must enable the MMU.The software routine operates by writing to
CP15 register 9 to force the victim pointer to a specific DCache
line and by using an LDR or LDM to
force the DCache to perform a lookup. This misses, assuming the
data was previously invalidated, and an eight-word linefill is performed
loading the cache line into the entry specified by the victim pointer.
When all the data has been loaded, it is then locked by writing
to CP15 register 9 to set the victim pointer base to be one higher than
the last entry written. All further linefills now occur in the range
victim base to 63.An example DCache lockdown routine is shown in Example 4.3. The example assumes
that the number of cache lines to be loaded is not known. The address
does not have to be cache line or word-aligned, although it is preferable
for future compatibility.
The LDR or LDM uses
VA format, because address aliasing is performed on the address.It is
advisable for the associated TLB entry to be locked into the TLB
to avoid page table walks during accesses of the locked data.
Example 4.3. DCache lockdown routine
ADRL 0,start_address ; address pointer
ADRL r1,end_address
MOV r2,#lockdown_base<<26 ; victim pointer
MCR p15,0,r2,c9,c0,0 ; write DCache victim and lockdown base
loop
LDR r3,[r0],#32 ; load DCache line, increment to next DCache line
;; do we need to increment the victim pointer?
;; test for segment 0, and if so, increment the victim pointer and
;; write the ICache victim and lockdown base.
AND r3,r0,#0x60 ; extract the segment bits from the address
CMP r3,#0x0 ; test for segment 0
ADDEQ r2,r2,#0x1<<26 ; if segment 0, increment victim pointer
MCREQ p15,0,r2,c9,c0,0 ; and write DCache victim and lockdown base
;; have we linefilled enough code?
;; test for the address pointer being less than or equal to the end_address
;; and if so, loop and perform another linefill
CMP r0,r1 ; test for less than or equal to end_address,
BLE loop ; if not, loop
;; have we exited with r3 pointing to segment 0?
;; if so, the ICache victim and lockdown base has already been set to one
;; higher than the last entry written.
;; if not, increment the victim pointer and write the ICache victim and
;; lockdown base.
CMP r3,#0x0 ; test for segments 1 to 3
ADDNE r2,r2,#0x1<<26 ; if address is segment 1 to 3,
MCRNE p15,0,r2,c9,c0,0 ; write DCache victim and lockdown base