ARM922T Technical Reference Manual 3.1. About the MMU

3.1. About the MMU

The ARM922T processor implements an enhanced ARM architecture v4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI core. The MMU is controlled from a single set of two-level page tables stored in main memory, that are enabled by the M bit in CP15 register 1, providing a single address translation and protection scheme. You can independently lock and flush the instruction and data TLBs in the MMU.

The MMU features are:

standard ARMv4 MMU mapping sizes, domains, and access protection scheme
mapping sizes are 1MB (sections), 64KB (large pages), 4KB (small pages), and 1KB (tiny pages)
access permissions for sections
access permissions for large pages and small pages can be specified separately for each quarter of the page (these quarters are called subpages)
16 domains implemented in hardware
64 entry instruction TLB and 64 entry data TLB
hardware page table walks
round-robin replacement algorithm (also called cyclic)
invalidate whole TLB, using CP15 register 8
invalidate TLB entry, selected by MVA, using CP15 register 8
independent lockdown of instruction TLB and data TLB, using CP15 register 10.

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