4.1. About the caches and write buffer

The ARM922T level-one memory system includes an Instruction Cache (ICache), a Data Cache (DCache), a write buffer, and a Physical Address (PA) TAG RAM to reduce the effect of main memory bandwidth and latency on performance.

The ARM922T implements separate 8KB instruction and 8KB data caches (ICache and DCache).

The caches have the following features:

The write buffer:

The ARM922T can be drained under software control and put into a low-power state until an interrupt occurs, using a CP15 MCR instruction (see Wait for interrupt).

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