Virtually-addressed 64-way associative cache.

8 words per line (32 bytes per line) with one valid bit and two dirty bits per line, allowing half-line write-backs.

Write-through and write-back cache operation (write-back caches are also known as copy-back caches), selected per memory region by the C and B bits in the MMU translation tables (for data cache only).

Pseudo-random or round-robin replacement, selectable using the RR bit in CP15 register 1.

Low-power CAM-RAM implementation.

Caches independently lockable with granularity of ¹/₆₄th of cache, which is 32 words (128 bytes).

To avoid TLB misses during write-back data eviction, and to reduce interrupt latency, the physical address corresponding to each data cache entry is stored in the PA TAG RAM for use during cache line write-backs, in addition to the VA TAG stored in the cache CAMs. This means that the MMU is not involved in cache write-back operations, removing the possibility of TLB misses related to the write-back address.

Cache maintenance operations to provide efficient cleaning of the entire data cache, and to provide efficient cleaning and invalidation of small regions of virtual memory. The latter allows ICache coherency to be efficiently maintained when small code changes occur, for example self-modifying code and changes to exception vectors.

has a 16-word data buffer

has a 4-address address buffer

can be drained under software control, using a CP15 MCR instruction (see Drain write buffer).