4.2. ICache

The ARM922T includes an 8KB ICache. The ICache has 256 lines of 32 bytes (8 words), arranged as a 64-way set-associative cache and uses MVAs, translated by CP15 register 13 (see Address translation), from the ARM9TDMI core.

The ICache implements allocate-on-read-miss. Random or round-robin replacement can be selected under software control using the RR bit (CP15 register 1, bit 14). Random replacement is selected at reset.

Instructions can also be locked in the ICache so that they cannot be overwritten by a linefill. This operates with a granularity of 1/64th of the cache, which is 32 words (128 bytes).

All instruction accesses are subject to MMU permission and translation checks. Instruction fetches that are aborted by the MMU do not cause linefills or instruction fetches to appear on the AMBA ASB interface.


For clarity, the I bit (bit 12 in CP15 register 1) is called the Icr bit throughout the following text. The C bit from the MMU translation table descriptor corresponding to the address being accessed is called the Ctt bit.

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