If the data for an MCR operation is not available inside the ARM9TDMI pipeline during its first Decode cycle, the ARM922T pipeline interlocks for one or more cycles until the data is available. An example of this is where the register being transferred is the destination from a preceding LDR instruction. In this situation the MCR instruction enters the Decode stage of the coprocessor pipeline, and remains there for a number of cycles before entering the Execute stage. Figure 7.4 gives an example of an interlocked MCR. In this example the MCR busy-waits the ARM9TDMI. When the instruction enters the Decode stage of the coprocessor pipeline, the coprocessor drives CHSDE[1:0] with WAIT. Due to an interlock in the ARM9TDMI, the instruction remains in Decode for an extra cycle. This is signaled to the coprocessor by nCPMREQ going HIGH, holding the instruction in the Decode stage of the coprocessor pipeline follower. The coprocessor signals WAIT to the ARM9TDMI during its second Decode cycle. The interlock in the ARM9TDMI resolves, nCPMREQ goes LOW, and the instruction moves from Decode into Execute.