ARM922T Technical Reference Manual 2.3.13. Register 9, cache lockdown register

2.3.13. Register 9, cache lockdown register

Register 9 is the cache lockdown register. The cache lockdown register is 0x0 on reset. The cache lockdown register allows software to control which cache line in the ICache or DCache respectively is loaded for a linefill and to prevent lines in the ICache or DCache from being evicted during a linefill, locking them into the cache.

There is a register for each of the ICache and DCache. The value of opcode_2 determines which cache register to access:

opcode_2 = 0x0 accesses the DCache register
opcode_2 = 0x1 accesses the ICache register.

The Opcode_1 and CRm fields should be zero.

Reading CP15 register 9 returns the value of the cache lockdown register, which is the base pointer for all cache segments.

Note

Only bits [31:26] are returned. Bits [25:0] are unpredictable.

Writing CP15 register 9 updates the cache lockdown register, both the base and the current victim pointer for all cache segments. Bits [25:0] should be zero.

The victim counter specifies the cache line to be used as the victim for the next linefill. This is incremented using either a random or round-robin replacement policy, determined by the state of the RR bit in register 1. The victim counter generates values in the range (base to 63). This locks lines with index values in the range (0 to base-1). If base = 0, there are no locked lines.

Writing to CP15 register 9 updates the base pointer and the current victim pointer. The next linefill uses, and then increments, the victim pointer. The victim pointer continues incrementing on linefills, and wraps around to the base pointer. For example, setting the base pointer to 0x3 prevents the victim pointer from selecting entries 0x0 to 0x2, locking them into the cache. Example 2.1 shows how you can load a cache line into ICache line 0 and lock it down.

Example 2.1. Load a cache line into ICache line 0 and lock it down

MCR to CP15 register 9, opcode_2 = 0x1, Victim=Base=0x0

MCR I prefetch. Assuming the ICache misses, a linefill occurs to line 0.

MCR to CP15 register 9, opcode_2 = 0x1, Victim=Base=0x1

More ICache linefills now occur into lines 1-63.

Example 2.2 shows how you can load a cache line into DCache line 0 and lock it down.

Example 2.2. Load a cache line into DCache line 0 and lock it down

MCR to CP15 register 9, opcode_2 = 0x0, Victim=Base=0x0

Data load (LDR/LDM). Assuming the DCache misses, a linefill occurs to line 0.

MCR to CP15 register 9, opcode_2 = 0x0, Victim=Base=0x1

More DCache linefills now occur into lines 1-63.

Note

Writing CP15 register 9, with the CRm field set to b0001, updates the current victim pointer only for the specified segment. Bits [31:26] specify the victim. Bits [7:5] specify the segment (for a 16KB cache). All other bits should be zero. This encoding is intended for debug use. You are not recommended to use this encoding.

Figure 2.7 shows the format of bits in register 9.

Figure 2.7. Register 9

Table 2.18 shows the instructions you can use to access the cache lockdown register.

Table 2.18. Accessing the cache lockdown register 9

Function	Data	Instruction
Read DCache lockdown base	Base	`MRC p15,0,Rd,c9,c0,0`
Write DCache victim and lockdown base	Victim=Base	`MCR p15,0,Rd,c9,c0,0`
Read ICache lockdown base	Base	`MRC p15,0,Rd,c9,c0,1`
Write ICache victim and lockdown base	Victim=Base	`MCR p15,0,Rd,c9,c0,1`

Copyright © 2000, 2001 ARM Limited. All rights reserved.	ARM DDI 0184B
Non-Confidential
PDF version