2.3.11. Register 7, cache operations register

Register 7 is a write-only register used to manage the ICache and DCache.

The cache operations provided by register 7 are described in Table 2.15.

Table 2.15. Function descriptions register 7

Function

Description

Invalidate cache

Invalidates all cache data, including any dirty data.[1] Use with caution.

Invalidate single entry using MVA

Invalidates a single cache line, discarding any dirty data.a Use with caution.

Clean D single entry using either index or MVA

Writes the specified cache line to main memory, if the line is marked valid and dirty, and marks the line as not dirty.a The valid bit is unchanged.

Clean and Invalidate D entry using either index or MVA

Writes the specified cache line to main memory, if the line is marked valid and dirty.a The line is marked not valid.

Prefetch cache line

Performs an ICache lookup of the specified MVA.

If the cache misses, and the region is cachable, a linefill is performed.

[1] Dirty data is data that has been modified in the cache but not yet written to main memory.

The function of each cache operation is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 7. Writing other opcode_2 or CRm values is unpredictable.

Reading from CP15 register 7 is unpredictable.

Table 2.16 shows instructions that you can use to perform cache operations with register 7.

Table 2.16. Cache operations register 7

Function

Data

Instruction

Invalidate ICache and DCache

SBZ

MCR p15,0,Rd,c7,c7,0

Invalidate ICache

SBZ

MCR p15,0,Rd,c7,c5,0

Invalidate ICache single entry (using MVA)

MVA format

MCR p15,0,Rd,c7,c5,1

Prefetch ICache line (using MVA)

MVA format

MCR p15,0,Rd,c7,c13,1

Invalidate DCache

SBZ

MCR p15,0,Rd,c7,c6,0

Invalidate DCache single entry (using MVA)

MVA format

MCR p15,0,Rd,c7,c6,1

Clean DCache single entry (using MVA)

MVA format

MCR p15,0,Rd,c7,c10,1

Clean and Invalidate DCache entry (using MVA)

MVA format

MCR p15,0,Rd,c7,c14,1

Clean DCache single entry (using index)

Index format

MCR p15,0,Rd,c7,c10,2

Clean and Invalidate DCache entry (using index)

Index format

MCR p15,0,Rd,c7,c14,2

Drain write buffer [1]

SBZ

MCR p15,0,Rd,c7,c10,4

Wait for interrupt [2]

SBZ

MCR p15,0,Rd,c7,c0,4

[1] Stops execution until the write buffer has drained.

[2] Stops execution in a LOW power state until an interrupt occurs.

The operations that you can carry out on a single cache line identify the line using the data passed in the MCR instruction. The data is interpreted using one of the formats shown in Figure 2.4 or Figure 2.5.

Figure 2.4. Register 7 MVA format

Figure 2.5. Register 7 index format

The use of register 7 is described in Chapter 4 Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM.

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