ARM922T Technical Reference Manual 2.3.14. Register 10, TLB lockdown register

2.3.14. Register 10, TLB lockdown register

Register 10 is the TLB lockdown register. The TLB lockdown register is 0x0 on reset. There is a TLB lockdown register for each of the TLBs, the value of opcode_2 determines which TLB register to access:

opcode_2 = 0x0 accesses the D TLB register
opcode_2 = 0x1 accesses the I TLB register.

Reading CP15 register 10 returns the value of the TLB lockdown counter base register, the current victim number, and the preserve bit (P bit). Bits [19:1] are unpredictable when read.

Writing CP15 register 10 updates the TLB lockdown counter base register, the current victim pointer, and the state of the preserve bit. Bits [19:1] should be zero when written.

Table 2.19 shows the instructions you can use to access the TLB lockdown register.

Table 2.19. Accessing the TLB lockdown register 10

Function	Data	Instruction
Read D TLB lockdown	TLB lockdown	`MRC p15,0,Rd,c10,c0,0`
Write D TLB lockdown	TLB lockdown	`MCR p15,0,Rd,c10,c0,0`
Read I TLB lockdown	TLB lockdown	`MRC p15,0,Rd,c10,c0,1`
Write I TLB lockdown	TLB lockdown	`MCR p15,0,Rd,c10,c0,1`

Figure 2.8 shows the format of bits in register 10.

Figure 2.8. Register 10

The entries in the TLBs are replaced using a round-robin replacement policy. This is implemented using a victim counter that counts from entry 0 up to 63, and then wraps back round to the base value and continues counting, wrapping around to the base value from 63 each time.

There are two mechanisms available for ensuring entries are not removed from the TLB:

Locking an entry down prevents it from being selected for overwriting during a table walk. You can do this by programming the base value to which the victim counter reloads. For example, if the bottom 3 entries (0–2) are to be locked down, you must program the base counter to 3.
You can preserve an entry during an Invalidate All instruction. You can do this by ensuring the P bit is set when the entry is loaded into the TLB. Examples that show how you can load a single entry into the I and D TLBs at location 0, make it immune to Invalidate All, and lock it down are shown in Example 2.3 and Example 2.4.

Example 2.3. Load a single entry into I TLB location 0, make it immune to Invalidate All and lock it down

MCR to CP15 register 10, opcode_2 = 0x1, Base Value = 0,

Current Victim = 0, P = 1

MCR I prefetch.

Assuming an I TLB miss occurs, then entry 0 is loaded.

MCR to CP15 register 10, opcode_2 = 0x1, Base Value = 1, Current Victim = 1,

P = 0

Example 2.4. Load a single entry into D TLB location 0, make it immune to Invalidate All and lock it down

MCR to CP15 register 10, opcode_2 = 0x0, Base Value = 0,

Current Victim = 0, P = 1

Data load (LDR/LDM) or store (STR/STM). Assuming a D TLB miss occurs, then entry 0 is loaded.

MCR to CP15 register 10, opcode_2 = 0x0, Base Value = 1, Current Victim = 1,

P = 0

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