| Copyright © 2000, 2001 ARM Limited. All rights reserved. | ARM DDI 0184B |
| Non-Confidential | |
 PDF version | |
| Home > Programmer’s Model > About the ARM9TDMI programmer’s model |
| |||
| Home > Programmer’s Model > About the ARM9TDMI programmer’s model | |||
The ARM9TDMI processor core implements ARM architecture v4T, and executes the ARM 32-bit instruction set and the compressed Thumb 16-bit instruction set. The programmer’s model is fully described in the ARM Architecture Reference Manual. The ARM9TDMI Technical Reference Manual gives implementation details, including instruction execution cycle times.
ARMv4T specifies a small number of implementation options. The options selected in the ARM9TDMI implementation are listed in Table 2.1. For comparison, the options selected for the ARM7TDMI implementation are also shown.
Table 2.1. ARM9TDMI implementation options
Processor core | Architecture | Data Abort model | Value stored by direct STR, STRT, and STM of PC |
|---|---|---|---|
ARM7TDMI | ARMv4T | Base updated | Address of instruction + 12 |
ARM9TDMI | ARMv4T | Base restored | Address of instruction + 12 |
The ARM9TDMI core is code-compatible with the ARM7TDMI, with two exceptions:
The ARM9TDMI core implements the base restored Data Abort model. This significantly simplifies the software Data Abort handler.
The ARM9TDMI core fully implements the instruction set extension spaces added to the ARM (32-bit) instruction set in ARMv4 and ARMv4T.
These differences are explained in more detail in the following sections:
| Copyright © 2000, 2001 ARM Limited. All rights reserved. | ARM DDI 0184B |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > About the ARM9TDMI programmer’s model |