2.3.5. Register 1, control register

This register contains the control bits of the ARM922T. All reserved bits must either be written with 0 or 1, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read. Use the following instructions to read and write this register:

MRC p15, 0, Rd, c1, c0, 0       ; read control register
MCR p15, 0, Rd, c1, c0, 0       ; write control register

All defined control bits are set to 0 on reset, except the V bit. The V bit is set to 0 at reset if the VINITHI pin is LOW, or 1 if the VINITHI pin is HIGH. The functions of the control bits are shown in Table 2.10.

Table 2.10. Control register 1 bit functions

Register

bits

Name

Function

Value

31

iA bit

Asynchronous clock select

See Table 2.11.

30

nF bit

notFastBus select

See Table 2.11.

29:15

-

Reserved

Read = Unpredictable.

Write = Should be zero.

14

RR bit

Round robin replacement

0 = Random replacement.

1 = Round-robin replacement.

13

V bit

Base location of exception

registers

0 = Low addresses = 0x00000000.

1 = High addresses = 0xFFFF0000.

12

I bit

ICache enable

0 = ICache disabled.

1 = ICache enabled.

11:10

-

Reserved

Read = 00.

Write = 00.

9

R bit

ROM protection

This bit modifies the MMU protection system. See Domain access control.

8

S bit

System protection

This bit modifies the MMU protection system. See Domain access control.

7

B bit

Endianness

0 = Little-endian operation.

1 = Big-endian operation.

6:3

-

Reserved

Read = 1111.

Write = 1111.

2

C bit

DCache enable

0 = DCache disabled.

1 = DCache enabled.

1

A bit

Alignment fault enable

Data address alignment fault checking.

0 = Fault checking disabled.

1 = Fault checking enabled.

0

M bit

MMU enable

0 = MMU disabled.

1 = MMU enabled.

Register 1 bits [31:30] select the clocking mode of the ARM922T, as shown in Table 2.11.

Table 2.11. Clocking modes

Clocking mode

iA

nF

FastBus mode

0

0

Synchronous

0

1

Reserved

1

0

Asynchronous

1

1

Enabling the MMU

You must take care with the address mapping of the code sequence used to enable the MMU (see Enabling the MMU).

See Enabling and disabling the ICache and Enabling and disabling the DCache and write buffer for the restrictions and the effects of having caches enabled with the MMU disabled.

Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DDI 0184B
Non-Confidential