This is a read-only register that contains information about the size and architecture of the caches, allowing operating systems to establish how to perform such operations as cache cleaning and lockdown. All ARMv4T and later cached processors contain this register, allowing RTOS vendors to produce future-proof versions of their operating systems.

You can access the cache type register by reading CP15 register 0 with the opcode_2 field set to 1. For example:

MRC p15,0,Rd,c0,c0,1     ; returns cache details

The format of the cache type register is shown in Figure 2.2.

The Dsize and Isize fields in the cache type register have the same format. This is shown in Figure 2.3.

The register values for the ARM922T cache type register are listed in Table 2.6.

Bits [28:25] indicate which major cache class the implementation falls into. 0x6 means that the cache provides:

The size of the cache is determined by the size field and the M bit. The M bit is 0 for the data and instruction caches. Bits [20:18] for the Data Cache (DCache) and bits [8:6] for the Instruction Cache (ICache) are the size field. Table 2.7 shows the cache size encoding.

The associativity of the cache is determined by the assoc field and the M bit. The M bit is 0 for the data and instruction caches. Bits [17:15] for the DCache and bits [5:3] for the ICache are the assoc field. Table 2.8 shows the cache associativity encoding.

The line length of the cache is determined by the len field. Bits [13:12] for the DCache and bits [1:0] for the ICache are the len field. Table 2.9 shows the line length encoding.