2.3.4. Register 0, cache type register

This is a read-only register that contains information about the size and architecture of the caches, allowing operating systems to establish how to perform such operations as cache cleaning and lockdown. All ARMv4T and later cached processors contain this register, allowing RTOS vendors to produce future-proof versions of their operating systems.

You can access the cache type register by reading CP15 register 0 with the opcode_2 field set to 1. For example:

MRC p15,0,Rd,c0,c0,1     ; returns cache details

The format of the cache type register is shown in Figure 2.2.

Figure 2.2. Cache type register format

ctype

The ctype field determines the cache type.

S bit

Specifies whether the cache is a unified cache or separate instruction and data caches.

Dsize

Specifies the size, line length, and associativity of the data cache.

Isize

Specifies the size, line length, and associativity of the instruction cache.

The Dsize and Isize fields in the cache type register have the same format. This is shown in Figure 2.3.

Figure 2.3. Dsize and Isize field format

size

The size field determines the cache size in conjunction with the M bit.

assoc

The assoc field determines the cache associativity in conjunction with the M bit.

M bit

The multiplier bit. Determines the cache size and cache associativity values in conjunction with the size and assoc fields.

len

The len field determines the line length of the cache.

The register values for the ARM922T cache type register are listed in Table 2.6.

Table 2.6. Cache type register format

Function

Register bits

Value

Reserved

31:29

0b000

ctype

28:25

0b0110

S

24

0b1 = Harvard cache

Dsize

Reserved

23:21

0b000

size

20:18

0b100 = 8KB

assoc

17:15

0b110 = 64-way

M

14

0b0

len

13:12

0b10 = 8 words per line (32 bytes)

Isize

Reserved

11:9

0b000

size

8:6

0b100 = 8KB

assoc

5:3

0b110 = 64-way

M

2

0b0

len

1:0

0b10 = 8 words per line (32 bytes)

Bits [28:25] indicate which major cache class the implementation falls into. 0x6 means that the cache provides:

The size of the cache is determined by the size field and the M bit. The M bit is 0 for the data and instruction caches. Bits [20:18] for the Data Cache (DCache) and bits [8:6] for the Instruction Cache (ICache) are the size field. Table 2.7 shows the cache size encoding.

Table 2.7. Cache size encoding (M=0)

size field

Cache size

0b000

512B

0b001

1KB

0b010

2KB

0b011

4KB

0b100

8KB

0b101

16KB

0b110

32KB

0b111

64KB

The associativity of the cache is determined by the assoc field and the M bit. The M bit is 0 for the data and instruction caches. Bits [17:15] for the DCache and bits [5:3] for the ICache are the assoc field. Table 2.8 shows the cache associativity encoding.

Table 2.8. Cache associativity encoding (M=0)

assoc field

Associativity

0b000

Direct mapped

0b001

2-way

0b010

4-way

0b011

8-way

0b100

16-way

0b101

32-way

0b110

64-way

0b111

128-way

The line length of the cache is determined by the len field. Bits [13:12] for the DCache and bits [1:0] for the ICache are the len field. Table 2.9 shows the line length encoding.

Table 2.9. Line length encoding

len field

Cache line length

00

2 words (8 bytes)

01

4 words (16 bytes)

10

8 words (32 bytes)

11

16 words (64 bytes)

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