When set, this bit prevents the ICache from performing a linefill on an ICache miss. Instead, a single word read is performed from the AMBA ASB interface. The memory region mapping is unchanged. This mode of operation is required for debug so that the memory image, as seen by the ARM9TDMI, can be read in a non-invasive manner. Cache hits from a cachable region read the instruction from the cache, and cache misses from a cachable region do not cause a linefill, but read a single instruction from memory.You must use the control bit disable ICache linefill instead of I force noncachable, because I force noncachable does not read from the cache on a cache hit.