The cachable behavior for a memory region is determined by the AND of the DCache enable in CP15 register 1 and the cachable bit of the MMU page table entry:

C = Ccr AND Ctt

Setting the D force noncachable bit effectively forces the C=0. This means all memory accesses are treated as single memory accesses on the AMBA ASB interface. A write that hits in the cache updates the cache. A read that hits in the cache is ignored, and the data read from the AMBA ASB interface does not update the cache.