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| Home > CP15 Test Registers > Test state register > Bit 1, D miss abort | |||
When DTLB page table walks are disabled, the DTLB miss causes
a Data Abort and indicates a translation fault in the DFSR. The
Data Abort handler then has to use a CP15 MCR instruction
to write a page table entry to the data TLB.It is a requirement
that the DCache and MMU is enabled when you disable hardware page
table walks, otherwise the behavior is unpredictable.