If the ICache is disabled, each instruction fetch results
in a separate nonsequential memory access on the AMBA ASB interface,
giving very low bus and memory performance. Therefore, you must
enable the ICache as soon as possible after reset.
If the ICache is enabled, an ICache lookup is performed for
each instruction fetch regardless of the setting of the Ctt bit
in the relevant MMU translation table descriptor:
If the required instruction is found
in the cache, the lookup is called a cache hit. If the instruction
fetch is a cache hit and Ctt=1, indicating a cachable region of memory,
then the instruction is returned from the cache to the ARM9TDMI
CPU core.
If the required instruction is not found in the
cache, the lookup is called a cache miss. If it is a cache miss
and Ctt=1, then an eight-word linefill is performed, possibly replacing
another entry. The entry to be replaced, called the victim, is chosen
from the entries that are not locked, using either a random or round-robin replacement
policy.If Ctt=0, indicating a noncachable region of memory, then
a single nonsequential memory access appears on the AMBA ASB interface.
Note
If Ctt=0, indicating a noncachable region of memory, then
the cache lookup results in a cache miss. The only way that it can
result in a cache hit is if software has changed the value of the
Ctt bit in the MMU translation table descriptor without invalidating
the cache contents. This is a programming error. The behavior in
this case is architecturally unpredictable and varies between implementations.
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