6.3.2. Transfer types

The AMBA ASB specification describes three transfer types that are encoded in BTRAN[1:0]. Table 6.3 shows these transfer types.

Table 6.3. AMBA ASB transfer types

BTRAN[1:0]Transfer typeDescription
00Address-only (A-TRAN)

Used when no data movement is required. The three main uses for address-only transfers are:

  • for IDLE cycles

  • for bus handover cycles

  • for speculative address decoding without committing to a data transfer.

10Nonsequential (N-TRAN)Used for single transfers or the first transfer of a burst. The address of the transfer is unrelated to the previous bus access.
11Sequential (S-TRAN)Used for successive transfers in burst. The address of a SEQUENTIAL transfer is always related to the previous transfer.

The ARM922T does not use N-TRAN cycles, instead it uses an A-TRAN cycle followed by a S-TRAN cycle for nonsequential transfers. This eases AMBA decoder design considerably, particularly for high-speed designs.

The output signals ASTB, BURST[1:0], and NCMAHB have been added to the ARM922T bus interface. They are necessary to support the AMBA AHB wrapper, but can also be used to provide optimized accesses in an AMBA ASB system:


This signal distinguishes between an IDLE cycle and the A-TRAN cycle of a nonsequential transfer. It is asserted with the same timing as AOUT[31:0], changing in phase 2. Usually a memory controller only commits to a transfer when it sees the S-TRAN cycle, perhaps only decoding the address during the A-TRAN cycle. ASTB is asserted in the preceding A-TRAN cycle, indicating that the current A-TRAN is followed by an S-TRAN, providing AGNT is HIGH on the next rising edge of BCLK.


This signal gives an indication of the length of a sequential burst, as shown in Table 6.4.

Table 6.4. Burst transfers

00No burst or undefined burst length
014-word burst
108-word burst
11No burst or undefined burst length

For linefills, BURST[1:0] indicates 8 words. For cache line evictions, BURST[1:0] indicates either 4 or 8 words. For all other transfers, BURST[1:0] indicates no burst or undefined burst length.

The meaning of the BURST[1:0] encoding is clarified when considered whether the transfer is a read or write. In this way you can distinguish between bufferable and nonbufferable STR/STM and table walks, as shown in Table 6.5.

Table 6.5. Use of WRITEOUT signal

BURST[1:0]WRITEOUTARM922T bus accessType
00ReadNC LDR/LDM/fetchNoncachable read
00WriteNCNB STR/STMNonbufferable write
01WriteWrite-back of 4 wordsBufferable write
10ReadLinefill of 8 wordsCachable read
10WriteWrite-back of 8 wordsBufferable write
11ReadTable walkCachable read
11WriteNCB/WT/WB miss STR/STMBufferable write

The BURST[1:0] signals change in phase 2 and are asserted in the phase when ASTB is asserted. BURST[1:0] then remains unchanged until the next transfer.


This signal indicates for noncached load multiples whether more words are requested as part of the current burst transfer. When HIGH this indicates more words are requested. When LOW, on the last S-TRAN of the burst, this indicates that the current transfer is the last word of the burst. It is asserted in phase 2 and is only valid if AGNT remains asserted throughout the transfer.

The following timing diagrams show the types of transfer that can be initiated by the ARM922T rev0:

Where the AREQ and AGNT signals and the responses from the ASB slave are not shown in these diagrams, it is assumed that AGNT is asserted and the ASB slave response is DONE.

Different slave responses and bus master handover are covered in the AMBA Specification (Rev 2.0). It is assumed that you are using the ARM922T macrocell within a multi-master ASB system, so unidirectional ASB timing diagrams are not provided.

Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DDI 0184B