7.2.1. Coprocessor handshake encoding

Table 7.1 shows how the handshake signals CHSDE[1:0] and CHSEX[1:0] are encoded.

Table 7.1. Handshake encoding

State

[1:0]

ABSENT

10

WAIT

00

GO

01

LAST

11

If you do not attach a coprocessor to the ARM922T, then the handshake signals must be driven with ABSENT.

If you attach multiple coprocessors to the interface, the handshaking signals can be combined by ANDing bit 1, and ORing bit 0. In the case of two coprocessors that have handshaking signals CHSDE1, CHSEX1 and CHSDE2, CHSEX2 respectively:

CHSDE[1]<= CHSDE1[1] AND CHSDE2[1]

CHSDE[0]<= CHSDE1[0] OR CHSDE2[0]

CHSEX[1]<= CHSEX1[1] AND CHSEX2[1]

CHSEX[0]<= CHSEX1[0] OR CHSEX2[0].

Consequently, if the coprocessor does not recognize a coprocessor instruction, it must drive CHSDE[1:0] and CHSEX[1:0] with ABSENT.

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