9.3.6. Actions of the ARM922T in debug state

When the ARM922T is in debug state, both memory interfaces indicate internal cycles. This allows the rest of the memory system to ignore the ARM9TDMI core and function as normal. Because the rest of the system continues operation, the ARM9TDMI core ignores aborts and interrupts.

The BIGEND signal must not be changed by the system while in debug state. If it changes there might be a synchronization problem, and the ARM922T processor (as seen by the programmer) changes without the knowledge of the debugger. The BnRES signal must also be held stable during debug. If the system applies reset to the ARM922T processor (BnRES is driven LOW), the state of the ARM922T changes without the knowledge of the debugger.

When instructions are executed in debug state, the ARM9TDMI core changes asynchronously to the memory system outputs (except for InMREQ, ISEQ, DnMREQ, and DSEQ that change synchronously from GCLK). For example, every time a new instruction is scanned into the pipeline, the instruction address bus changes. If the instruction is a load or store operation, the data address bus changes as the instruction executes. Although this is asynchronous, it does not affect the system, because both interfaces indicate internal cycles. You must take care when designing the memory controller to ensure that this does not become a problem.

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