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The EmbeddedICE macrocell register map is shown in Table 9.15.
Table 9.15. ARM9TDMI EmbeddedICE macrocell register map
Address | Width | Function |
|---|---|---|
00000 | 4 | Debug control |
00001 | 5 | Debug status |
00010 | 8 | Vector catch control |
00100 | 6 | Debug comms control |
00101 | 32 | Debug comms data |
01000 | 32 | Watchpoint 0 address value |
01001 | 32 | Watchpoint 0 address mask |
01010 | 32 | Watchpoint 0 data value |
01011 | 32 | Watchpoint 0 data mask |
01100 | 9 | Watchpoint 0 control value |
01101 | 8 | Watchpoint 0 control mask |
10000 | 32 | Watchpoint 1 address value |
10001 | 32 | Watchpoint 1 address mask |
10010 | 32 | Watchpoint 1 data value |
10011 | 32 | Watchpoint 1 data mask |
10100 | 9 | Watchpoint 1 control value |
10101 | 8 | Watchpoint 1 control mask |
The general arrangement of the EmbeddedICE macrocell is shown in Figure 9.11.
As an example, if a watchpoint is requested on a particular
memory location but the data value is irrelevant, you can program
the data mask register to 0xFFFF_FFFF, all bits
set to 1. This ensures that the entire data bus value is ignored.
| Copyright © 2000, 2001 ARM Limited. All rights reserved. | ARM DDI 0184B |
| Non-Confidential | |
| PDF version | |
| Home > Debug Support > EmbeddedICE macrocell > Register map |