ARM922T Technical Reference Manual 9.13.5. Debug status register

9.13.5. Debug status register

The debug status register is five bits wide. If this register is accessed for a write (with the read/write bit set HIGH), the status bits are written. If it is accessed for a read (with the read/write bit LOW), the status bits are read.

Figure 9.15. Debug status register

The function of the bits in the debug status register are shown in Table 9.18.

Table 9.18. Debug status register bit functions

Bits	Function
4	Allows ITBIT to be read. This enables the debugger to determine what state the processor is in, and therefore determine the instructions to execute.
3	Allows the state of the SYSCOMP bit from the core (synchronized to TCK) to be read. This allows the debugger to determine that a memory access from the debug state has completed.
2	Allows the state of the core interrupt enable signal, IFEN, to be read. Because the capture clock for the scan chain might be asynchronous to the processor clock, the DBGACK output from the core is synchronized before being used to generate the IFEN status bit.
1:0	Allow the values on the synchronized versions of DBGRQ and DBGACK to be read.

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