9.16.2. Communications using the comms channel

There are two methods of communicating using the comms channel:

Sending a message to the debugger and Receiving a message from the debugger detail their usage.

Sending a message to the debugger

When the processor wishes to send a message to the debugger, it must check that the comms data write register is free for use by finding out if the W bit of the debug comms control register is clear:

  • If the W bit is set, previously written data has not been read by the debugger. The processor must continue to poll the control register until the W bit is clear.

  • If W bit is clear, the comms data write register is clear.

When the W bit is clear, a message can be written by a register transfer to coprocessor 14. As the data transfer occurs from the processor to the comms data write register, the W bit is set in the debug comms control register.

The debugger sees a synchronized version of both the R and W bit when it polls the debug comms control register through the JTAG interface. When the debugger sees the W bit is set, it can read the comms data write register and scan the data out. The action of reading this data register clears the debug comms control register W bit. At this point, the communications process can begin again.

As an alternative to polling, the debug comms channel can be interrupt driven by connecting the ARM922T COMMRX and COMMTX signals to the systems interrupt controller.

Receiving a message from the debugger

Message transfer from the debugger to the processor is similar to sending a message to the debugger. In this case, the debugger polls the R bit of the debug comms control register:

  • if the R bit is LOW, the comms data read register is free, and data can be placed there for the processor to read

  • if the R bit is set, previously deposited data has not yet been collected, so the debugger must wait.

When the comms data read register is free, data can be written using the JTAG interface. The action of this write sets the R bit in the debug comms control register.

When the processor polls this register, it sees a GCLK synchronized version. If the R bit is set, there is data waiting to be collected. You can read this data read using an MRC instruction to coprocessor 14. The action of this load clears the R bit in the debug comms control register. When the debugger polls this register and sees that the R bit is clear, the data has been taken, and the process can now be repeated.

Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DDI 0184B
Non-Confidential