Using this manual

This document is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for an introduction to the ARM922T.

Chapter 2 Programmer’s Model

Read this chapter for a description of the programmer’s model for the ARM922T.

Chapter 3 Memory Management Unit

Read this chapter for a description of the memory management unit and the memory interface, including descriptions of the instruction and data interfaces.

Chapter 4 Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM

Read this chapter for descriptions of cache, write buffer, and PA TAG RAM operation.

Chapter 5 Clock Modes

Read this chapter for a description of the processor clock modes.

Chapter 6 Bus Interface Unit

Read this chapter for a description of the bus interface unit and the AMBA ASB and AHB interface.

Chapter 7 Coprocessor Interface

Read this chapter for a description of the ARM922T coprocessor interface.

Chapter 8 Trace Interface Port

Read this chapter for a description of the Trace Interface Port of the ARM922T.

Chapter 9 Debug Support

Read this chapter for a description of the debug interface.

Chapter 10 TrackingICE

Read this chapter for a description of how the ARM922T uses TrackingICE mode.

Chapter 11 AMBA Test Interface

Read this chapter for a description of the AMBA test interface.

Chapter 12 Instruction Cycle Summary and Interlocks

Read this chapter for details of instruction cycle times. This chapter contains timing diagrams for interlock timing.

Chapter 13 AC Characteristics

Read this chapter for a description of the timing parameters used in the ARM922T.

Appendix A Signal Descriptions

Read this chapter for a detailed description of the signals used in the ARM922T.

Appendix B CP15 Test Registers

Read this chapter for a detailed description of the CP15 test register used in the ARM922T.

Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DDI 0184B
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