ARM ® 720T TechnicalReference Manual

Rev 3


Table of Contents

Preface
About this document
Intended audience
Using this manual
Conventions
Further reading
ARM publications
Other publications
Feedback
Feedback on the ARM720T
Feedback on the ARM720T documentation
1. Introduction
1.1. About the ARM720T
1.2. Coprocessors
1.3. About the instruction set
1.3.1. Format summary
1.3.2. ARM instruction set
1.3.3. Thumb instruction set
2. Programmer’s Model
2.1. Processor operating states
2.1.1. Switching state
2.2. Memory formats
2.2.1. Big‑endian format
2.2.2. Little‑endian format
2.3. Instruction length
2.4. Data types
2.5. Operating modes
2.5.1. Changing modes
2.6. Registers
2.6.1. The ARM state register set
2.6.2. The Thumb state register set
2.6.3. The relationship between ARM and Thumb stateregisters
2.6.4. Accessing high registers in Thumb state
2.7. The program status registers
2.7.1. The condition code flags
2.7.2. The control bits
2.7.3. Reserved bits
2.8. Exceptions
2.8.1. Action on entering an exception
2.8.2. Action on leaving an exception
2.8.3. Exception entry and exit summary
2.8.4. Fast interrupt request
2.8.5. Interrupt request
2.8.6. Abort
2.8.7. Software interrupt
2.8.8. Undefined instruction
2.8.9. Exception vectors
2.8.10. Exception priorities
2.8.11. Exception restrictions
2.9. Relocation of low virtual addressesby the FCSE PID
2.10. Reset
2.11. Implementation-defined behavior ofinstructions
2.11.1. Indexed Addressing on a Data Abort
2.11.2. Early termination
3. Configuration
3.1. About configuration
3.1.1. Compatibility
3.1.2. Notation
3.2. Internal coprocessor instructions
3.3. Registers
3.3.1. Register 0, ID register
3.3.2. Register 1, control register
3.3.3. Register 2, translation table base register
3.3.4. Register 3, domain access control register
3.3.5. Register 4, reserved
3.3.6. Register 5, fault status register
3.3.7. Register 6, Fault Address Register
3.3.8. Register 7, cache operations
3.3.9. Register 8, TLB operations
3.3.10. Registers 9 to 12, reserved
3.3.11. Register 13, process identifier
3.3.12. Registers 14-15, reserved
4. Instruction and Data Cache
4.1. About the instruction and data cache
4.1.1. IDC operation
4.1.2. Cachable bit
4.1.3. Read-lock-write
4.2. IDC validity
4.2.1. Software IDC flush
4.2.2. Doubly‑mapped space
4.3. IDC enable, disable, and reset
4.4. IDC disable for secure applications
5. Write Buffer
5.1. About the write buffer
5.1.1. Bufferable bit
5.2. Write buffer operation
5.2.1. Bufferable write
5.2.2. Unbufferable write
5.2.3. Read-lock-write
6. Memory Management Unit
6.1. About the MMU
6.1.1. Memory accesses
6.1.2. Domains
6.1.3. TLB
6.1.4. Effect of reset
6.2. MMU program accessible registers
6.3. Address translation process
6.3.1. Translation table base
6.3.2. Level 1 fetch
6.4. Level 1 descriptor
6.5. Page table descriptor
6.6. Section descriptor
6.7. Translating section references
6.8. Level 2 descriptor
6.9. Translating small page references
6.10. Translating large page references
6.11. MMU faults and CPU aborts
6.12. Fault address and fault status registers
6.13. Domain access control
6.14. Fault checking sequence
6.14.1. Alignment fault
6.14.2. Translation fault
6.14.3. Domain fault
6.14.4. Permission fault
6.15. External aborts
6.15.1. Cachable reads (linefetches)
6.15.2. Buffered writes
6.16. Interaction of the MMU, IDC, and writebuffer
6.16.1. Enabling the MMU
6.16.2. Disabling the MMU
7. Debug Interface
7.1. About the debug interface
7.1.1. Debug extensions
7.1.2. Pullup resistors
7.1.3. Instruction register
7.2. Debug systems
7.2.1. Debug host
7.2.2. Protocol converter
7.2.3. Debug target
7.3. Entering debug state
7.3.1. Entering debug state on breakpoint
7.3.2. Entering debug state on watchpoint
7.3.3. Entering debug state on debug-request
7.4. Scan chains and JTAG interface
7.4.1. Scan limitations
7.4.2. The JTAG state machine
7.5. Reset
7.6. Public instructions
7.6.1. EXTEST (0000)
7.6.2. SCAN_N (0010)
7.6.3. INTEST (1100)
7.6.4. IDCODE (1110)
7.6.5. BYPASS (1111)
7.6.6. CLAMP (0101)
7.6.7. HIGHZ (0111)
7.6.8. CLAMPZ (1001)
7.6.9. RESTART (0100)
7.6.10. SAMPLE/PRELOAD (0011)
7.7. Test data registers
7.7.1. Bypass register
7.7.2. ARM7TDM device identification coderegister
7.7.3. Instruction register
7.7.4. Scan chain select register
7.7.5. Scan chains 0, 1, 2, and 15
7.7.6. Scan chain 0
7.7.7. Scan chain 1
7.7.8. Scan chain 2
7.7.9. Scan chain 15
7.8. ARM7TDM core clocks
7.8.1. Clock switch during debug
7.9. Determining the core and system state
7.9.1. Determining ARM or Thumb state
7.9.2. Determining the state of the core
7.9.3. Determining system state
7.9.4. Determining system control coprocessor state
7.9.5. Exit from debug state
7.10. The PC during debug
7.10.1. Breakpoint
7.10.2. Watchpoint
7.10.3. Watchpoint with another exception
7.10.4. Debug request
7.10.5. System‑speed access
7.10.6. Summary of return address calculations
7.11. Priorities and exceptions
7.11.1. Breakpoint with Prefetch Abort
7.11.2. Interrupt
7.11.3. Data Aborts
7.12. Scan interface timing
7.13. Scan and debug signals used by theembedded trace logic
8. EmbeddedICE Logic
8.1. About EmbeddedICE Logic
8.1.1. Disabling EmbeddedICE
8.1.2. EmbeddedICE timing
8.2. The watchpoint registers
8.2.1. Programming and reading watchpoint registers
8.2.2. Using the mask registers
8.2.3. The control registers
8.3. Programming breakpoints
8.3.1. Hardware breakpoints
8.3.2. Software breakpoints
8.4. Programming watchpoints
8.4.1. Programming restriction
8.5. The debug control register
8.5.1. DBGRQ
8.5.2. DBGACK
8.5.3. INTDIS
8.6. Debug status register
8.7. Coupling breakpoints and watchpoints
8.7.1. CHAINOUT
8.7.2. RANGEOUT
8.8. Debug communications channel
8.8.1. Debug communications channel registers
8.8.2. Communications using the comms channel
8.8.3. Message transfer
9. Bus Clocking
9.1. About the ARM720T bus interface
9.1.1. Standard mode
9.1.2. Fastbus extension
9.2. Fastbus extension
9.2.1. Using BWAIT
9.3. Standard mode
9.3.1. Memory access
9.3.2. Synchronous and asynchronous modes
10. AMBA Interface
10.1. About the AMBA interface
10.2. ASB bus interface signals
10.3. Cycle types
10.3.1. Single‑word memory access
10.3.2. Sequential accesses
10.3.3. Bus accesses
10.4. Addressing signals
10.5. Memory request signals
10.6. Data signal timing
10.7. Slave response signals
10.7.1. BERROR
10.7.2. BWAIT
10.8. Maximum sequential length
10.9. Read-lock-write
10.10. Little-endian and big-endian operation
10.10.1. Little‑endian format
10.10.2. Big‑endian format
10.10.3. Word operations
10.10.4. Halfword operations
10.10.5. Byte operations
10.11. Multi-master operation
10.11.1. Arbitration
10.12. Bus master handover
10.13. Default bus master
11. AMBA Test
11.1. Slave operation, test mode
11.2. ARM720T test mode
11.3. ARM7TDM core test mode
11.4. RAM test mode
11.5. TAG test mode
11.6. MMU test mode
11.7. Test register mapping
12. Trace Interface Port
12.1. About the ETM
12.2. ETM interface
12.2.1. ETMCLK gating for power saving
A. Signal Descriptions
A.1. AMBA interface signals
A.2. Coprocessor interface signals
A.3. JTAG signals
A.4. Debugger signals
A.5. Embedded trace macrocell interfacesignals
A.6. Miscellaneous signals
A.7. Additional signal outputs

List of Figures

1. Key to timing diagram conventions
1.1. Block diagram
1.2. ARM instruction set formats
1.3. Thumb instruction set formats
2.1. Big-endian addresses of bytes withwords
2.2. Little-endian addresses of bytes withwords
2.3. Register organization in ARM state
2.4. Register organization in Thumb state
2.5. Mapping of Thumb state registersonto ARM state registers
2.6. Program status register format
3.1. MRC and MCR bit pattern
3.2. ID register read
3.3. ID register write
3.4. Register 1 read
3.5. Register 1 write
3.6. Register 2
3.7. Register 3
3.8. Register 4
3.9. Register 5
3.10. Register 6
3.11. Register 13 with opcode_2=0
3.12. Register 13 with opcode_2=1
6.1. Translation table base register
6.2. Accessing the translation table firstlevel descriptors
6.3. Level 1 descriptors
6.4. Section translation
6.5. Page table entry, level 2 descriptor
6.6. Small page translation
6.7. Large page translation
6.8. Domain access control register format
6.9. Sequence for checking faults
7.1. Typical debug system
7.2. ARM7TDM scan chain arrangement
7.3. Test access port (TAP) controllerstate transitions
7.4. ID code register format
7.5. Input scan cell
7.6. Clock switching on entry to debugstate
7.7. Scan general timing
7.8. Reset period timing
7.9. Output enable and disable times dueto HIGHZ TAP instruction
7.10. Output enable and disable times dueto data scanning
8.1. ARM7TDMI TAP controller and EmbeddedICE
8.2. EmbeddedICE block diagram
8.3. Watchpoint control value and maskformat
8.4. Debug control register format
8.5. Debug status register format
8.6. Debug control and status registerstructure
8.7. Debug comms control register
9.1. Conceptual device clocking usingthe fastbus extension
9.2. Conceptual device clocking in standardmode
9.3. Relationship of FCLK and BCLK insynchronous mode
10.1. Simple single-cycle access
10.2. Simple sequential access
10.3. Minimum interval between bus accesses
10.4. Use of the BWAIT pin to stop ARM720T for1 BCLK cycle
10.5. Little‑endian addresses of byteswithin words
10.6. Big-endian addresses of bytes withinwords
10.7. Bus master handover
11.1. Running a test vector on the processorcore
11.2. State machine for ARM720T and ARM7TDMI test
11.3. State machine for RAM test mode
11.4. State machine for TAG test mode
11.5. State machine for MMU test mode
12.1. ETM interface signal timing
12.2. ETMCLK power saving

List of Tables

1.1. Key to tables
1.2. ARM instruction summary
1.3. Addressing mode 2
1.4. Addressing mode 2 (privileged)
1.5. Addressing mode 3
1.6. Addressing mode 4 (load)
1.7. Addressing mode 4 (store)
1.8. Addressing mode 5
1.9. Operand 2
1.10. Fields
1.11. Condition fields
1.12. Thumb instruction summary
2.1. ARM720T modes of operation
2.2. PSR mode bit values
2.3. Exception entry and exit
2.4. Exception vector addresses
3.1. Cache and MMU control register
3.2. Cache operation
3.3. TLB operations
6.1. MMU program accessible registers
6.2. Interpreting level 1 descriptor bits [1:0]
6.3. Interpreting access permission (AP) bits
6.4. Interpreting page table entry bits 1:0
6.5. Priority encoding of fault status
6.6. Interpreting access bits in domain access control register
6.7. Valid MMU, IDC and write buffer combinations
7.1. Scan chain number allocation
7.2. ARM720T scan interface timing
7.3. Scan chain 0, signals and positions
7.4. Scan and debug signals used by the ETM
8.1. Function and mapping of EmbeddedICE registers
8.2. MAS[1:0] signal encoding
8.3. IFEN signal control
10.1. BTRAN[1:0] encoding
11.1. RAM test mode address packet bit positions
11.2. TAG test mode TAG CTL packet bit positions
11.3. Status packet bit positions bits [31:0]
11.4. Control packet bit positions bits [31:0]
A.1. AMBA signal descriptions
A.2. Coprocessor interface signal descriptions
A.3. JTAG signal descriptions
A.4. Debugger signal descriptions
A.5. ETM interface signal descriptions
A.6. Miscellaneous signal descriptions

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This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A September2000 First release
Copyright © ARM Limited1997, 1998, 2000. All rights reserved. ARM DDI 0192A
Non-Confidential