ARM® PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual

Revision: r1p4


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on this book
1. Introduction
1.1. About the ARM PrimeCell SSP (PL022)
1.1.1. Features of the PrimeCell SSP
1.1.2. Programmable parameters
1.1.3. SPI features
1.1.4. Microwire features
1.1.5. Texas Instruments synchronous serial interface features
1.2. Product revisions
2. Functional Overview
2.1. PrimeCell SSP overview
2.2. PrimeCell SSP functional description
2.2.1. AMBA APB interface
2.2.2. Register block
2.2.3. Clock prescaler
2.2.4. Transmit FIFO
2.2.5. Receive FIFO
2.2.6. Transmit and receive logic
2.2.7. Interrupt generation logic
2.2.8. DMA interface
2.2.9. Synchronizing registers and logic
2.3. PrimeCell SSP operation
2.3.1. Interface reset
2.3.2. Configuring the SSP
2.3.3. Enable PrimeCell SSP operation
2.3.4. Clock ratios
2.3.5. Programming the SSPCR0 Control Register
2.3.6. Programming the SSPCR1 Control Register
2.3.7. Frame format
2.3.8. Texas Instruments synchronous serial frame format
2.3.9. Motorola SPI frame format
2.3.10. Motorola SPI Format with SPO=0, SPH=0
2.3.11. Motorola SPI Format with SPO=0, SPH=1
2.3.12. Motorola SPI Format with SPO=1, SPH=0
2.3.13. Motorola SPI Format with SPO=1, SPH=1
2.3.14. National Semiconductor Microwire frame format
2.3.15. Examples of master and slave configurations
2.3.16. PrimeCell DMA interface
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Summary of PrimeCell SSP registers
3.3. Register descriptions
3.3.1. Control register 0, SSPCR0
3.3.2. Control register 1, SSPCR1
3.3.3. Data register, SSPDR
3.3.4. Status register, SSPSR
3.3.5. Clock prescale register, SSPCPSR
3.3.6. Interrupt mask set or clear register, SSPIMSC
3.3.7. Raw interrupt status register, SSPRIS
3.3.8. Masked interrupt status register, SSPMIS
3.3.9. Interrupt clear register, SSPICR
3.3.10. DMA control register, SSPDMACR
3.3.11. Peripheral identification registers, SSPPeriphID0-3
3.3.12. PrimeCell identification registers, SSPPCellID0-3
3.4. Interrupts
3.4.1. SSPRXINTR
3.4.2. SSPTXINTR
3.4.3. SSPRORINTR
3.4.4. SSPRTINTR
3.4.5. SSPINTR
4. Programmer’s Model for Test
4.1. PrimeCell SSP test harness overview
4.2. Scan testing
4.3. Test registers
4.3.1. Test control register, SSPTCR
4.3.2. Integration test input register, SSPITIP
4.3.3. Integration test output register, SSPITOP
4.3.4. Test data register, SSPTDR
4.4. Integration testing of block inputs
4.4.1. Intra-chip inputs
4.4.2. Primary inputs
4.5. Integration testing of block outputs
4.5.1. Intra-chip outputs
4.5.2. Primary outputs
4.6. Integration test summary
A. Signal Descriptions
A.1. AMBA APB signals
A.2. On-chip signals
A.3. Signals to pads
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. PrimeCell SSP block diagram
2.1. PrimeCell SSP block diagram
2.2. Texas Instruments synchronous serial frame format, single transfer
2.3. Texas Instruments synchronous serial frame format, continuous transfer
2.4. Motorola SPI frame format, single transfer, with SPO=0 and SPH=0
2.5. Motorola SPI frame format, continuous transfer, with SPO=0 and SPH=0
2.6. Motorola SPI frame format with SPO=0 and SPH=1, single and continuous transfers
2.7. Motorola SPI frame format, single transfer, with SPO=1 and SPH=0
2.8. Motorola SPI frame format, continuous transfer, with SPO=1 and SPH=0
2.9. Motorola SPI frame format with SPO=1 and SPH=1, single and continuous transfers
2.10. Microwire frame format, single transfer
2.11. Microwire frame format, continuous transfers
2.12. Microwire frame format, SSPFSSIN input setup and hold requirements
2.13. PrimeCell SSP master coupled to a PL022 slave
2.14. PrimeCell SSP master coupled to an SPI slave
2.15. SPI master coupled to a PrimeCell SSP slave
2.16. DMA transfer waveforms
3.1. SSPCR0 Register bit assignments
3.2. SSPCR1 Register bit assignments
3.3. SSPDR Register bit assignments
3.4. SSPSR Register bit assignments
3.5. SSPCPSR Register bit assignments
3.6. SSPIMSC Register bit assignments
3.7. SSPRIS Register bit assignments
3.8. SSPMIS Register bit assignments
3.9. SSPICR Register bit assignments
3.10. SSPDMACR Register bit assignments
3.11. Peripheral identification Register bit assignments
3.12. SSPPeriphID0 Register bit assignments
3.13. SSPPeriphID1 Register bit assignments
3.14. SSPPeriphID2 Register bit assignments
3.15. SSPPeriphID3 Register bit assignments
3.16. PrimeCell identification Register bit assignments
3.17. SSPPCellID0 Register bit assignments
3.18. SSPPCellID1 Register bit assignments
3.19. SSPPCellID2 Register bit assignments
3.20. SSPPCellID3 Register bit assignments
4.1. SSPTCR Register bit assignments
4.2. SSPITIP Register bit assignments
4.3. SSPITOP Register bit assignments
4.4. SSPTDR Register bit assignments
4.5. Input integration test harness
4.6. Output integration test harness, intra-chip outputs
4.7. Primary outputs routed to primary inputs
4.8. Output integration test harness, primary outputs

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Revision History
Revision A6 September 2000First release
Revision B19 March 2001Second release
Revision C15 June 2001Third release
Revision D31 July 2001Fourth release
Revision E30 January 2009Fifth release
Revision F01 November 2011Sixth release
Revision G04 November 2011Seventh release
Revision H29 January 2016Eighth release
Copyright © 2000-2001, 2009, 2011, 2016. All rights reserved.ARM DDI 0194H
Non-ConfidentialID012616