ARM926EJ-S™ Technical Reference Manual

Revision: r0p5


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the ARM926EJ-S processor
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Summary of ARM926EJ-S system control coprocessor (CP15) registers
2.2.1. Addresses in an ARM926EJ-S system
2.2.2. Accessing CP15 registers
2.3. Register descriptions
2.3.1. ID Code, Cache Type, and TCM Status Registers, c0
2.3.2. Control Register c1
2.3.3. Translation Table Base Register c2
2.3.4. Domain Access Control Register c3
2.3.5. Register c4
2.3.6. Fault Status Registers c5
2.3.7. Fault Address Register c6
2.3.8. Cache Operations Register c7
2.3.9. TLB Operations Register c8
2.3.10. Cache Lockdown and TCM Region Registers c9
2.3.11. TLB Lockdown Register c10
2.3.12. Register c11 and c12
2.3.13. Process ID Register c13
2.3.14. Register c14
2.3.15. Test and Debug Register c15
3. Memory Management Unit
3.1. About the MMU
3.1.1. Access permissions and domains
3.1.2. Translated entries
3.1.3. MMU program accessible registers
3.2. Address translation
3.2.1. Translation table base
3.2.2. First-level fetch
3.2.3. First-level descriptor
3.2.4. Section descriptor
3.2.5. Coarse page table descriptor
3.2.6. Fine page table descriptor
3.2.7. Translating section references
3.2.8. Second-level descriptor
3.2.9. Translating large page references
3.2.10. Translating small page references
3.2.11. Translating tiny page references
3.3. MMU faults and CPU aborts
3.3.1. Fault address and fault status registers
3.4. Domain access control
3.5. Fault checking sequence
3.5.1. Alignment faults
3.5.2. Translation faults
3.5.3. Domain faults
3.5.4. Permission faults
3.6. External aborts
3.6.1. Enabling the MMU
3.6.2. Disabling the MMU
3.7. TLB structure
4. Caches and Write Buffer
4.1. About the caches and write buffer
4.2. Write buffer
4.3. Enabling the caches
4.4. TCM and cache access priorities
4.5. Cache MVA and Set/Way formats
5. Tightly-Coupled Memory Interface
5.1. About the tightly-coupled memory interface
5.2. TCM interface signals
5.2.1. Data interface signals
5.2.2. Instruction TCM signals
5.2.3. Differences between DTCM and ITCM
5.3. TCM interface bus cycle types and timing
5.3.1. Zero wait state timing
5.3.2. DMA access to zero wait state TCM
5.3.3. Multi-cycle access timing
5.4. TCM programmer’s model
5.4.1. Enabling the ITCM
5.4.2. Enabling the DTCM
5.4.3. Disabling the ITCM
5.4.4. Disabling the DTCM
5.4.5. Cacheable and bufferable attributes
5.5. TCM interface examples
5.5.1. Zero-wait-state RAM example
5.5.2. Producing byte writable memory using word writable RAM
5.5.3. Multiple banks of RAM example
5.5.4. Sequential ROM example
5.5.5. DMA interface example
5.5.6. Integrating RAM test logic
5.6. TCM access penalties
5.7. TCM write buffer
5.8. Using synchronous SRAM as TCM memory
5.9. TCM clock gating
6. Bus Interface Unit
6.1. About the bus interface unit
6.2. Supported AHB transfers
6.2.1. Memory map
6.2.2. Transfer size
6.2.3. Mapping of level one and level two AHB attributes
6.2.4. Byte and halfword accesses
6.2.5. AHB system considerations
6.2.6. AHB clocking
6.2.7. External Abort limitations
7. Noncacheable Instruction Fetches
7.1. About noncacheable instruction fetches
7.1.1. Uses of noncacheable code
7.1.2. Self modifying code
7.1.3. AHB behavior
8. Coprocessor Interface
8.1. About the ARM926EJ-S external coprocessor interface
8.1.1. Coprocessor instructions
8.2. LDC/STC
8.3. MCR/MRC
8.3.1. Interlocked MCR
8.4. CDP
8.5. Privileged instructions
8.6. Busy-waiting and interrupts
8.7. CPBURST
8.8. CPABORT
8.9. nCPINSTRVALID
8.10. Connecting multiple external coprocessors
Instruction Memory Barrier. Instruction Memory Barrier
Instruction Memory Barrier.1. About the instruction memory barrier operation
Instruction Memory Barrier.2. IMB operation
Instruction Memory Barrier.2.1. Clean the DCache
Instruction Memory Barrier.2.2. Drain the write buffer
Instruction Memory Barrier.2.3. Synchronize data and instruction streams in level two AHB subsystems
Instruction Memory Barrier.2.4. Invalidate the ICache
Instruction Memory Barrier.2.5. Flush the prefetch buffer
Instruction Memory Barrier.3. Example IMB sequences
10. Embedded Trace Macrocell Support
10.1. About Embedded Trace Macrocell support
10.1.1. FIFOFULL
11. Debug Support
11.1. About debug support
11.1.1. Debug clocks
11.1.2. Scan chain 15
12. Power Management
12.1. About power management
12.1.1. Dynamic power management (wait for interrupt mode)
12.1.2. Static power management (leakage control)
A. Signal Descriptions
A.1. Signal properties and requirements
A.2. AHB related signals
A.3. Coprocessor interface signals
A.4. Debug signals
A.5. JTAG signals
A.6. Miscellaneous signals
A.7. ETM interface signals
A.8. TCM interface signals
B. CP15 Test and Debug Registers
B.1. About the Test and Debug Registers
B.1.1. Debug Override Register
B.1.2. Debug and Test Address Register
B.1.3. Trace Control Register
B.1.4. MMU test operations
B.1.5. Cache Debug Control Register
B.1.6. MMU Debug Control Register
B.1.7. Memory Region Remap Register
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. ARM926EJ-S block diagram
1.2. ARM926EJ-S interface diagram, part one
1.3. ARM926EJ-S interface diagram, part two
2.1. CP15 MRC and MCR bit pattern
2.2. Cache Type Register format
2.3. Dsize and Isize field format
2.4. TCM Status Register format
2.5. Control Register format
2.6. TTBR format
2.7. Register c3 format
2.8. FSR format
2.9. Register c7 MVA format
2.10. Register c7 Set/Way format
2.11. Register c8 MVA format
2.12. Cache Lockdown Register c9 format
2.13. TCM Region Register c9 format
2.14. TLB Lockdown Register format
2.15. Process ID Register format
2.16. Context ID Register format
3.1. Translation Table Base Register
3.2. Translating page tables
3.3. Accessing translation table first-level descriptors
3.4. First-level descriptor
3.5. Section descriptor
3.6. Coarse page table descriptor
3.7. Fine page table descriptor
3.8. Section translation
3.9. Second-level descriptor
3.10. Large page translation from a coarse page table
3.11. Small page translation from a coarse page table
3.12. Tiny page translation from a fine page table
3.13. Sequence for checking faults
4.1. Generic virtually indexed virtually addressed cache
4.2. ARM926EJ-S cache associativity
4.3. ARM926EJ-S cache Set/Way/Word format
5.1. Multi-cycle data side TCM access
5.2. Instruction side zero wait state accesses
5.3. Data side zero wait state accesses
5.4. Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS
5.5. DMA access interaction with normal DTCM accesses
5.6. Generating a single wait state for ITCM accesses using IRWAIT
5.7. State machine for generating a single wait state
5.8. Loopback of SEQ to produce a single cycle wait state
5.9. Cycle timing of loopback circuit
5.10. DMA with single wait state for nonsequential accesses
5.11. Cycle timing of circuit with DMA and single wait state for nonsequential accesses
5.12. Zero wait state RAM example
5.13. Byte-banks of RAM example
5.14. Optimizing for power
5.15. Optimizing for speed
5.16. TCM subsystem that uses wait states for nonsequential accesses
5.17. Cycle timing of circuit that uses wait states for non sequential accesses
5.18. TCM subsystem that uses the DMA interface
5.19. TCM test access using BIST
6.1. Multi-layer AHB system example
6.2. Multi-AHB system example
6.3. AHB clock relationships
8.1. Producing a coprocessor clock
8.2. Coprocessor clocking
8.3. LDC/STC cycle timing
8.4. MCR/MRC cycle timing
8.5. Interlocked MCR
8.6. Latecanceled CDP
8.7. Privileged instructions
8.8. Busy waiting and interrupts
8.9. CPBURST and CPABORT timing
8.10. Arrangement for connecting two coprocessors
12.1. Deassertion of STANDBYWFI after an IRQ interrupt
12.2. Logic for stopping ARM926EJ-S clock during wait for interrupt
B.1. CP15 MRC and MCR bit pattern
B.2. Rd format for selecting main TLB entry
B.3. Rd format for accessing MVA tag of main or lockdown TLB entry
B.4. Rd format for accessing PA and AP data of main or lockdown TLB entry
B.5. Write to the data RAM
B.6. Rd format for selecting lockdown TLB entry
B.7. Cache Debug Control Register format
B.8. MMU Debug Control Register format
B.9. Memory Region Remap Register format
B.10. Memory region attribute resolution

List of Tables

2.1. CP15 register summary
2.2. Address types in ARM926EJ-S
2.3. CP15 abbreviations
2.4. Reading from register c0
2.5. Register 0, ID code
2.6. Ctype encoding
2.7. Cache size encoding (M=0)
2.8. Cache associativity encoding (M=0)
2.9. Line length encoding
2.10. Example Cache Type Register format
2.11. Control bit functions register c1
2.12. Effects of Control Register on caches
2.13. Effects of Control Register on TCM interface
2.14. Domain access control defines
2.15. FSR bit field descriptions
2.16. FSR status field encoding
2.17. Function descriptions register c7
2.18. Cache operations c7
2.19. Register c8 TLB operations
2.20. Cache Lockdown Register instructions
2.21. Cache Lockdown Register L bits
2.22. TCM Region Register instructions
2.23. TCM Region Register c9
2.24. TCM Size field encoding
2.25. Programming the TLB Lockdown Register
2.26. FCSE PID Register operations
2.27. Context ID register operations
3.1. MMU program-accessible CP15 registers
3.2. First-level descriptor bits
3.3. Interpreting first-level descriptor bits [1:0]
3.4. Section descriptor bits
3.5. Coarse page table descriptor bits
3.6. Fine page table descriptor bits
3.7. Second-level descriptor bits
3.8. Interpreting page table entry bits [1:0]
3.9. Priority encoding of fault status
3.10. FAR values for multi-word transfers
3.11. Domain access control register, access control bits
3.12. Interpreting access permission (AP) bits
4.1. CP15 c1 I and M bit settings for the ICache
4.2. Page table C bit settings for the ICache
4.3. CP15 c1 C and M bit settings for the DCache
4.4. Page table C and B bit settings for the DCache
4.5. Instruction access priorities to the TCM and cache
4.6. Data access priorities to the TCM and cache
4.7. Values of S and NSETS
5.1. Relationship between DMDMAEN, DRDMACS, and DRIDLE
6.1. Supported HBURST encodings
6.2. IHPROT[3:0] and DHPROT[3:0] attributes
8.1. Handshake signal encoding
8.2. CPBURST encoding
11.1. Scan chain 15 format
11.2. Scan chain 15 mapping to CP15 registers
A.1. AHB related signals
A.2. Coprocessor interface signals
A.3. Debug signals
A.4. JTAG signals
A.5. Miscellaneous signals
A.6. ETM interface signals
A.7. TCM interface signals
B.1. Debug Override Register
B.2. Trace Control Register bit assignments
B.3. MMU test operation instructions
B.4. Encoding of the main TLB entry-select bit fields
B.5. Encoding of the TLB MVA tag bit fields
B.6. Encoding of the TLB entry PA and AP bit fields
B.7. Main TLB mapping to MMUxWD
B.8. Encoding of the lockdown TLB entry-select bit fields
B.9. Cache Debug Control Register bit assignments
B.10. MMU Debug Control Register bit assignments
B.11. Memory Region Remap Register instructions
B.12. Encoding of the Memory Region Remap Register
B.13. Encoding of the remap fields

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A26 September 2001First release
Revision B29 January 2002Second release
Revision C5 December 2003Third release. Includes r0p5 changes. Defects corrected.
Revision D26 January 2004Fourth release. Includes r0p4. Technically identical to previous release.
Revision E16 June 2008Changes for r0p5 release, and other enhancements..
Copyright © 2001-2008 ARM Limited. All rights reserved.ARM DDI 0198E
Non-Confidential