2.3.8. Register 5, Access Permission Registers

There are four access permission registers. These contain the access permission bits for the instruction and data protection regions. The opcode_2 field of the MCR/MRC instruction determines whether the standard or extended registers are accessed, and if the instruction or data access permissions are accessed. To read and write the extended registers:

MRC p15, 0, Rd, c5, c0, 2; read data access permission bits
MRC p15, 0, Rd, c5, c0, 3; read instruction access permission bits
MCR p15, 0, Rd, c5, c0, 2; write data access permission bits
MCR p15, 0, Rd, c5, c0, 3; write instruction access permission bits

The format for the access permission bits in instruction and data areas is the same, and is shown in Table 2.12.

Table 2.12. Programming instruction and data access permission bits (extended)   

Register bits

Function

[31:28]

Ap7[3:0] bits for area 7

[27:24]

Ap6[3:0] bits for area 6

[23:20]

Ap5[3:0] bits for area 5

[19:16]

Ap4[3:0] bits for area 4

[15:12]

Ap3[3:0] bits for area 3

[11:8]

Ap2[3:0] bits for area 2

[7:4]

Ap1[3:0] bits for area 1

[3:0]

Ap0[3:0] bits for area 0

The values of the IApn[3:0] and DApn[3:0] bits define the access permission for each area of memory, n. Table 2.13 shows the encoding.

Table 2.13. Access permission encoding (extended) 

I/DApn[3:0]

Access permission

Privileged

User

b0000No accessNo access
b0001Read/write accessNo access
b0010Read/write accessRead-only
b0011Read/write accessRead/write access
b0100UNPUNP
b0101Read-onlyNo access
b0110Read-onlyRead-only
b0111UNPUNP
b1xxxUNPUNP

The following instructions are supported for backwards compatibility with existing ARM processors with memory protection, and access the standard registers:

MRC p15, 0, Rd, c5, c0, 0; read data access permission bits
MRC p15, 0, Rd, c5, c0, 1; read instruction access permission bits
MCR p15, 0, Rd, c5, c0, 0; write data access permission bits
MCR p15, 0, Rd, c5, c0, 1; write instruction access permission bits

Table 2.14 shows the data format for these registers.

Table 2.14. Instruction and data access permission bits (standard) 

Register bits

Function

[15:14]

Ap7[1:0] bits for area 7

[13:12]

Ap6[1:0] bits for area 6

[11:10]

Ap5[1:0] bits for area 5

[9:8]

Ap4[1:0] bits for area 4

[7:6]

Ap3[1:0] bits for area 3

[5:4]

Ap2[1:0] bits for area 2

[3:2]

Ap1[1:0] bits for area 1

[1:0]

Ap0[1:0] bits for area 0

The values of the IApn[1:0] and DApn[1:0] bits define the access permission for each area of memory, n. Table 2.15 shows the encoding.

Table 2.15. Access permission encoding (standard)

I/DApn[1:0]

Access permission

Privileged

User

b00No accessNo access
b01Read/write accessNo access
b10Read/write accessRead-only
b11Read/write accessRead/write access

Note

On reset, the values of IApn and DApn bits are undefined. However, because on reset the protection unit is disabled, this is as though all areas are set to privileged mode read/write access and User read/write access. Therefore, you must program the access permission registers before you enable the protection unit.

If the access permissions are initially programmed using the extended access permissions (see Table 2.13), and then reprogrammed using the standard access permissions (see Table 2.15), the access permissions applied are as if Apn[3:2] are programmed to b00 in Table 2.13.

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