A.1. Timing diagrams

The timing diagrams in this section are:

Each timing diagram is followed by a table showing timing parameters. All figures are expressed as percentages of the CLK period at maximum operating frequency.

Note

The figures quoted are relative to the rising clock edge after the clock skew for internal buffering has been added. Inputs given a 0% hold figure therefore require a positive hold relative to the top-level clock input. The amount of hold required is equivalent to the internal clock skew.

Figure A.1 shows the clock, reset, and AHB enable timing parameters.

Figure A.1. Clock, reset, and AHB enable timing

Table A.1 shows the timing parameter definitions for clock, reset, and AHB enable.

Table A.1. Timing parameter definitions for clock, reset, and AHB enable 

Symbol

Parameter

Min

Max

Tcyc

CLK cycle time

100%

-

Tishen

HCLKEN input setup to rising CLK

85%

-

Tihhen

HCLKEN input hold from rising CLK

0%

-

Tisrst

HRESETn de-assertion input setup to rising CLK

90%

-

Tihrst

HRESETn de-assertion input hold from rising CLK

0%

-

Figure A.2 shows the AHB bus request and grant related timing parameters.

Figure A.2. AHB bus request and grant related timing

Table A.2 shows Table A.2 the parameter definitions for AHB bus request and grant timing.

Table A.2. Parameter definitions for AHB bus request and grant timing 

Symbol

Parameter

Min

Max

Tovreq

Rising CLK to HBUSREQ valid

-

30%

Tohreq

HBUSREQ hold time from rising CLK

0%

-

Tovlck

Rising CLK to HLOCK valid

-

30%

Tohlck

HLOCK hold time from rising CLK

0%

-

Tisgnt

HGRANT input setup to rising CLK

50%

-

Tihgnt

HGRANT input hold from rising CLK

0%

-

Figure A.3 shows the AHB bus master timing parameters.

Figure A.3. AHB bus master timing

Table A.3 shows the parameter definitions for AHB bus master timing.

Table A.3. Parameter definitions for AHB bus master timing 

Symbol

Parameter

Min

Max

Tovtr

Rising CLK to HTRANS[1:0] valid

-

30%

Tohtr

HTRANS[1:0] hold time from rising CLK

0%

-

Tova

Rising CLK to HADDR[31:0] valid

-

30%

Toha

HADDR[31:0] hold time from rising CLK

0%

-

Tovctl

Rising CLK to AHB control signals valid

-

30%

Tohctl

AHB control signals hold time from rising CLK

0%

-

Tovwd

Rising CLK to HWDATA[31:0] valid

-

30%

Tohwd

HWDATA[31:0] hold time from rising CLK

0%

-

Tisrdy

HREADY input setup to rising CLK

50%

-

Tihrdy

HREADY input hold from rising CLK

0%

-

Tisrsp

HRESP[1:0] input setup to rising CLK

50%

-

Tihrsp

HRESP[1:0] input hold from rising CLK

0%

-

Tisrd

HRDATA[31:0] input setup to rising CLK

40%

-

Tihrd

HRDATA[31:0] input hold from rising CLK

0%

-

Figure A.4 shows the coprocessor interface timing parameters.

Figure A.4. Coprocessor interface timing

Table A.4 shows the parameter definitions for coprocessor interface timing.

Table A.4. Parameter definitions for coprocessor interface timing 

Symbol

Parameter

Min

Max

Tovcpen

Rising CLK to CPCLKEN valid

-

30%

Tohcpen

CPCLKEN hold time from rising CLK

0%

-

Tovcpid

Rising CLK to CPINSTR[31:0] valid

-

30%

Tohcpid

CPINSTR[31:0] hold time from rising CLK

0%

-

Tovcpctl

Rising CLK to transaction control valid

-

30%

Tohcpctl

Transaction control hold time from rising CLK

0%

-

Tiscphs

Coprocessor handshake input setup to rising CLK

50%

-

Tihcphs

Coprocessor handshake input hold from rising CLK

0%

-

Tovcplc

Rising CLK to CPLATECANCEL valid

-

30%

Tohcplc

CPLATECANCEL hold time from rising CLK

0%

-

Tovcpps

Rising CLK to CPPASS valid

-

30%

Tohcpps

CPPASS hold time from rising CLK

0%

-

Tovcprd

Rising CLK to CPDOUT[31:0] valid

-

30%

Tohcprd

CPDOUT[31:0] hold time from rising CLK

0%

-

Tiscpwr

CPDIN[31:0] input setup to rising CLK

50%

-

Tihcpwr

CPDIN[31:0] input hold from rising CLK

0%

-

Figure A.5 shows the debug interface timing parameters.

Figure A.5. Debug interface timing

Table A.5 shows the parameter definitions for debug interface timing.

Table A.5. Parameter definitions for debug interface timing 

Symbol

Parameter

Min

Max

Tovdbgack

Rising CLK to DBGACK valid

-

60%

Tohdbgack

DBGACK hold time from rising CLK

0%

-

Tovdbgrng

Rising CLK to DBGRNG[1:0] valid

-

80%

Tohdbgrng

DBGRNG[1:0] hold time from rising CLK

0%

-

Tovdbgrqi

Rising CLK to DBGRQI valid

-

45%

Tohdbgrqi

DBGRQI hold time from rising CLK

0%

-

Tovdbgstat

Rising CLK to DBGINSTREXEC valid

-

30%

Tohdbgstat

CLK hold time from rising DBGINSTREXEC

0%

-

Tovdbgcomm

Rising CLK to communication channel outputs valid

-

60%

Tohdbgcomm

Communication channel outputs hold time from rising CLK

0%

-

Tisdbgen

DBGEN input setup to rising CLK

35%

-

Tihdbgen

DBGEN input hold from rising CLK

0%

-

Tisedbgrq

EDBRQ input setup to rising CLK

20%

-

Tihedbgrq

EDBRQ input hold from rising CLK

0%

-

Tisdbgext

DBGEXT input setup to rising CLK

15%

-

Tihdbgext

DBGEXT input hold from rising CLK

0%

-

Tisiebkpt

DBGIEBKPT input setup to rising CLK

50%

-

Tihiebkpt

DBGIEBKPT input hold from rising CLK

0%

-

Tisdewpt

DBGDEWPT input setup to rising CLK

50%

-

Tihdewpt

DBGDEWPT input hold from rising CLK

0%

-

Figure A.6 shows the JTAG interface timing parameters.

Figure A.6. JTAG interface timing

Table A.6 shows the parameter definitions for JTAG interface timing.

Table A.6. Parameter definitions for JTAG interface timing 

Symbol

Parameter

Min

Max

Tovir

Rising CLK to DBGIR[3:0] valid

-

25%

Tohir

DBGIR[3:0] hold time from rising CLK

0%

-

Tovdbgsm

Rising CLK to debug state valid

-

30%

Tohdbgsm

Debug state hold time from rising CLK

0%

-

Tovtdoen

Rising CLK to DBGnTDOEN valid

-

40%

Tohtdoen

DBGnTDOEN hold time from rising CLK

0%

-

Tovsdin

Rising CLK to DBGSDIN valid

-

20%

Tohsdin

DBGSDIN hold time from rising CLK

0%

-

Tovtdo

Rising CLK to DBGTDO valid

-

65%

Tohtdo

DBGTDO hold time from rising CLK

0%

-

Tisntrst

DBGnTRST de-asserted input setup to rising CLK

25%

-

Tihntrst

DBGnTRST input hold from rising CLK

0%-

Tistdi

Tap state control input setup to rising CLK

25%

-

Tihtdi

Tap state control input hold from rising CLK

0%

-

Tistcken

DBGTCKEN input setup to rising CLK

50%

-

Tihtcken

DBGTCKEN input hold from rising CLK

0%

-

Tistapid

TAPID[3:0] input setup to rising CLK

35%

-

Tihtapid

TAPID[3:0] input hold from rising CLK

0%

-

A combinatorial path timing parameter exists from the DBGSDOUT input to DBGTDO output, as shown in Figure A.7.

Figure A.7. DBGSDOUT to DBGTDO timing

Table A.7 shows the parameter definitions for DBGSDOUT to DBGTDO timing.

Table A.7. Parameter definitions for DBGSDOUT to DBGTDO timing 

Symbol

Parameter

Min

Max

Ttdsd

DBGTDO delay from DBGSDOUTBS changing

-

30%

Ttdsh

DBGTDO hold time from DBGSDOUTBS changing

0%

-

Figure A.8 shows the exception and configuration timing parameters.

Figure A.8. Exception and configuration timing

Table A.8 shows the parameter definitions for exception and configuration timing.

Table A.8. Parameter definitions for exception and configuration timing 

Symbol

Parameter

Min

Max

Tovbigend

Rising CLK to BIGENDOUT valid

-

30%

Tohbigend

BIGENDOUT hold time from rising CLK

0%

-

Tisint

Interrupt input setup to rising CLK

15%

-

Tihint

Interrupt input hold from rising CLK

0%

-

Tishivecs

VINITHI input setup to rising CLK

90%

-

Tihhivecs

VINITHI input hold from rising CLK

0%

-

Tisinitram

INITRAM input setup to rising CLK

90%

-

Tihinitram

INITRAM input hold from rising CLK

0%

-

Note

The VINTHI and INITRAM signals are specified as 90% of the cycle because it is for input configuration during reset and can be considered static.

Figure A.9 shows the TCM interface timing parameters.

Figure A.9. TCM interface timing

Table A.9 shows the parameter definitions for TCM interface timing.

Table A.9. Parameter definitions for TCM interface timing 

Symbol

Parameter

Min

Max

Tovatcm

Rising CLK to TCMAdrs[17:0] valid

-90%
Tohatcm

TCMAdrs[17:0] hold time from rising CLK

0%-
Toventcm

Rising CLK to TCMEn valid

-90%
Tohentcm

TCMEn hold time from rising CLK

0%-
Tovtcmctl

Rising CLK to TCM control signals valid

-90%
Tohtcmctl

TCM control signals hold time from rising CLK

0% 
Tistcmrd

TCMRData[31:0] input setup to rising CLK

30%-
TihtcmrdTCMRData[31:0] input hold from rising CLK0%-
Tovtcmwd

Rising CLK to TCMWData[31:0] valid

-90%
Tohtcmwd

TCMWData[31:0] hold time from rising CLK

0%-

Figure A.10 shows the ETM interface timing parameters.

Figure A.10. ETM interface timing

Table A.10 shows the parameter definitions for ETM interface timing.

Table A.10. Parameter definitions for ETM interface timing 

Symbol

Parameter

Min

Max

Tovetminst

Rising CLK to ETM instruction interface valid

-

30%

Tohetminst

ETM instruction interface hold time from rising CLK

0%

-

Tovetmictl

Rising CLK to ETM instruction control valid

-

30%

Tohetmictl

ETM instruction control hold time from rising CLK

0%

-

Tovetmstat

Rising CLK to INSTREXEC valid

-

30%

Tohetmstat

INSTREXEC hold time from rising CLK

0%

-

Tovetmdata

Rising CLK to ETM data interface valid

-

30%

Tohetmdata

ETM data interface hold time from rising CLK

0%

-

Tovetmnwait

Rising CLK to nWAIT valid

-

30%

Tohetmnwait

nWAIT hold time from rising CLK

0%

-

Tovetmdctl

Rising CLK to ETM data control valid

-

30%

Tohetmdctl

ETM data control hold time from rising CLK

0%

-

Tovetmcfg

Rising CLK to ETM configuration valid

-

30%

Tohetmcfg

ETM configuration hold time from rising CLK

0%

-

Tovetmcpif

Rising CLK to ETM coprocessor signals valid

-

30%

Tohetmcpif

ETM coprocessor signals hold time from rising CLK

0%

-

Tovetmdbg

Rising CLK to ETM debug signals valid

-

30%

Tohetmdbg

ETM debug signals hold time from rising CLK

0%

-

Tisetmen

EN input setup to rising CLK

50%

-

Tihetmen

EN input hold from rising CLK

0%

-

Tisfifofull

ETMFIFOFULL input setup to rising CLK

50%

-

Tihfifofull

ETMFIFOFULL input hold from rising CLK

0%

-
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