The instruction and data Tightly-Coupled Memories (TCMs) are placed outside the ARM946E-S processor boundary. This enables greater flexibility in the memory attached to the ARM946E-S processor. The memories used must support single-cycle accesses from the ARM946E-S processor. They must be capable of returning data to the ARM9E-S core in a single cycle. This requirement applies to both the Instruction TCM and Data TCM. They are normally realized using synchronous SRAM.The Instruction TCM and Data TCM can both be of any size from 0 bytes to 1MB, although to ease implementation the size must be an integer power of two. The minimum size for a TCM when present is 4KB. The Instruction TCM and Data TCM can have different sizes.

To enable the Instruction TCM to be initialized, and for access to literal tables during execution, the data interface of the ARM9E-S core must be able to access the Instruction TCM. This means that the ARM946E-S processor must multiplex the instruction and data addresses before entering the Instruction TCM. It also means that the instruction data is routed to both the instruction and data interfaces of the core. See Instruction TCM accesses for details of this data and address multiplexing.

Figure 5.1 shows a typical TCM read cycle. The enable signal, TCMEn, is either ITCMEn or DTCMEn, depending on whether instruction or data memory is being accessed. The TCM interface signals are described in TCM interface signals.

The Instruction TCM is located at address 0x00000000 in the memory map. This simplifies the implementation of the design by removing the requirement for complex address comparators on both the instruction and data interfaces of the ARM9E-S core to generate the chip select logic for the Instruction TCM.