9.2.3. ARM946E-S debug target

The ARM9E-S core within the ARM946E-S processor has hardware extensions that ease debugging at the lowest level. The debug extensions:

Figure 9.3 shows the following major blocks of the ARM9E-S:

ARM9E-S CPU core

This includes hardware support for debug.

EmbeddedICE-RT logic

This is a set of registers and comparators used to generate debug exceptions (such as breakpoints). This unit is described in Overview of EmbeddedICE-RT.

TAP controller

This controls the action of the scan chains using a JTAG serial interface.

Figure 9.3. ARM9E-S block diagram

The ARM9E-S debug model is extended within the ARM946E-S processor by the addition of scan chain 15. This is used for debug access to the CP15 register bank, to enable you to configure the system state within the ARM946E-S processor while in debug state, for instance to enable or disable the TCM before performing a debug load or store.

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