9.4.4. Scan Chain Debug Status Register

In situations where the AHB clock frequency is significantly less than the debugger clock frequency, cache maintenance operations initialized by the debug scan chain (scan chain 15) might not be registered by the ARM946E-S processor.

This situation can be prevented by providing status information to the debugger. Cache maintenance operations (cache flush and cache clean) are read/write accesses. By reading back from the same scan chain register address that initiated the maintenance operation, a status bit is returned to the debugger. If the bit is set, the operation has been completed and the debug sequence can continue. If the bit is cleared, the requested operation has not been completed.

The status bit is implemented for the debug scan chain operations shown in Table 9.7.

Table 9.7. Status bit mapping of scan chain 15 address field to CP15 registers 

Address [37]

[36:33]

[32]

Register number

Register name

Register type

0

b0111

0

C7.FD

Flush data cache

Read/write

0

b0111

1

C7.FI

Flush instruction cache

Read/write

0

b1110

0

C7.FD.s

Flush data cache single (uses C15.C.Ind)

Read/write

0

b1110

1

C7.FI.s

Flush instruction cache single (uses C15.C.Ind)

Read/write

1

b1010

1

C7.CD.s

Clean data cache single (uses C15.C.Ind)

Read/write

0

b1011

1

C15.IT

Instruction tag read/write (uses C15.C.Ind)

Read/write

1

b1110

1

C15.Mem

TCM BIST control

Read/write

Table 9.7 shows the complete list of operations that can be initiated from the debug scan chain.

Table 9.8 shows the status bit associated with each cache maintenance operation.

Table 9.8. Correlation between status bits and cache operations 

Status bitsCache maintenance operation
[31:19]Unpredictable
[18]Flush instruction cache busy
[17]Flush instruction cache single busy
[16:11]Unpredictable
[10]Flush data cache busy
[9]Flush data cache single busy
[8]Unpredictable
[7]Clean data cache single busy
[6:0]Unpredictable
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