10.2.1. ARM946E-S INTEST wrapper

In addition to the auto-inserted scan chains, the ARM946E-S processor optionally includes a dual-purpose INTEST scan chain wrapper. This facilitates ATPG and provides an additional method for activating BIST of the compiled RAM.

ATPG

You can use the INTEST scan chain to enable an ATPG tool to access the ARM946E-S processor top-level inputs and outputs in an embedded design. This wrapper adds a scan source for each ARM946E-S processor input and a capture cell for each output. The ATPG tools use this scan chain in addition to the ones created by scan insertion, to test the logic from a given input pin to any register that it connects to, and from any registers whose outputs end up at a pin.

Note

The order of this scan chain is predetermined and must be maintained through synthesis and place and route of the macrocell.

BIST activation

To enable the BIST hardware to be activated by scan means, the INTEST wrapper has a second operational mode. When the SERIALEN input is true, serialized MCR instructions to initiate BIST operation are scanned in through this scan chain. The instructions target the CP15 BIST Register. After a predetermined number of clock cycles (depending on the size of the test), the appropriate MRC instruction is scanned in to read the BIST Control Register to check the test result. The INTEST wrapper enables the full range of BIST operations to be applied as detailed in BIST of memory arrays. The flow for generating the serialized patterns from ARM assembler source is supplied with the ARM946E-S implementation scripts.

TESTMODE

This signal is used to prevent the cache from being inadvertently flushed when scan patterns are shifted through the scan chains. It must only be asserted during scan test of the ARM946E-S processor.

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