2.3.14. Register 15, BIST Control Registers

Register 15 gives you access to the test features included within the ARM946E-S processor. Memory BIST operations are initiated by writes to this register. BIST results and status are evaluated by reading this register. The formats of the TAG BIST Control Register, TCM BIST Control Register, and the Cache RAM BIST Control Register are the same.

Table 2.24 shows the register map for CP15 register 15 BIST-related instructions.

Table 2.24. Register 15, BIST instructions 

Register

Read

Write

TAG BIST Control Register

MRC p15, 0, Rd, c15, c0, 1

MCR p15, 0, Rd, c15, c0, 1

TCM BIST Control Register

MRC p15, 1, Rd, c15, c0, 1

MCR p15, 1, Rd, c15, c0, 1

Cache RAM BIST Control Register

MRC p15, 2, Rd, c15, c0, 1

MCR p15, 2, Rd, c15, c0, 1

Table 2.25 shows CP15 register 15 implementation-specific BIST instructions.

Table 2.25. Register 15, implementation-specific BIST instructions 

Register

Read

Write

Instruction TAG BIST Address Register

MRC p15, 0, Rd, c15, c0, 2

MCR p15, 0, Rd, c15, c0, 2

Instruction TAG BIST General Register

MRC p15, 0, Rd, c15, c0, 3

MCR p15, 0, Rd, c15, c0, 3

Data TAG BIST Address Register

MRC p15, 0, Rd, c15, c0, 6

MCR p15, 0, Rd, c15, c0, 6

Data TAG BIST General Register

MRC p15, 0, Rd, c15, c0, 7

MCR p15, 0, Rd, c15, c0, 7

Instruction TCM BIST Address Register

MRC p15, 1, Rd, c15, c0, 2

MCR p15, 1, Rd, c15, c0, 2

Instruction TCM BIST General Register

MRC p15, 1, Rd, c15, c0, 3

MCR p15, 1, Rd, c15, c0, 3

Data TCM BIST Address Register

MRC p15, 1, Rd, c15, c0, 6

MCR p15, 1, Rd, c15, c0, 6

Data TCM BIST General Register

MRC p15, 1, Rd, c15, c0, 7

MCR p15, 1, Rd, c15, c0, 7

Instruction Cache RAM BIST Address Register

MRC p15, 2, Rd, c15, c0, 2

MCR p15, 2, Rd, c15, c0, 2

Instruction Cache RAM BIST General Register

MRC p15, 2, Rd, c15, c0, 3

MCR p15, 2, Rd, c15, c0, 3

Data Cache RAM BIST Address Register

MRC p15, 2, Rd, c15, c0, 6

MCR p15, 2, Rd, c15, c0, 6

Data Cache RAM BIST General Register

MRC p15, 2, Rd, c15, c0, 7

MCR p15, 2, Rd, c15, c0, 7

Note

It is recommended that you do not write application code that relies on the presence of the BIST Address and General Registers. Support for these registers in future versions of the ARM946E-S processor is not guaranteed.

Table 2.26 shows the format of the BIST Control Register.

Table 2.26. BIST Control Register bit definitions 

Register bit Meaning when written Meaning when read
[31: 21] Instruction BIST size Instruction BIST size
[20] Reserved (SBZ) Instruction BIST complete flag
[19] Reserved (SBZ) Instruction BIST fail flag
[18] Instruction BIST enable Instruction BIST enable
[17] Instruction BIST pause Instruction BIST pause
[16] Instruction BIST run strobe Instruction BIST running flag
[15: 5] Data BIST size Data BIST size
[4] Reserved (SBZ) Data BIST complete flag
[3] Reserved (SBZ) Data BIST fail flag
[2] Data BIST enable Data BIST enable
[1] Data BIST pause Data BIST pause
[0] Data BIST run strobe Data BIST running flag

Note

The pause and size bits of this register are not supported in all implementations.

The BIST size field determines the size of the BIST operation. The value written to this field, N, is decoded as follows:

BIST size in bytes = 2N+2

Table 2.27 shows some examples.

Table 2.27. BIST size encodings examples 

Instruction RAM BIST size [31:21]NSize of test
b000000 00001 (minimum)18 bytes
b000000 00100464 bytes
b000000 001117512 bytes
b000000 0100081 KB
b000000 01010104 KB
b000000 0111115128 KB
b000000 11000 (maximum)2464 MB
Copyright © 2001-2003, 2007 ARM Limited. All rights reserved.ARM DDI 0201D
Non-Confidential