10.3.3. BIST Address and General Registers

The BIST Control Register enables you to perform standard BIST operations on each RAM block and to optionally specify the size of the test. Additional registers are required, however, to provide the following functionality:

This additional functionality is most useful for debugging faulty silicon during production test. The exception to this is the start address for a BIST operation. It is possible to perform periodic BIST operations on RAM during the execution of a program rather than in one go. This requires a start address that is incremented by the size of the test each time a test is activated.

Note

It is recommended that you do not write application code that relies on the presence of the BIST Address and General Registers. ARM Limited. does not guarantee to support these registers in future versions of the ARM946E-S processor.

Table 10.1 and Table 10.2 show how the registers are used. The pause bits from the BIST Control Register provide extra decode of these registers.

Table 10.1. Instruction BIST Address and General Registers

BIST Register

IBIST pause

Read

Write

IBIST Address Register

0

IBIST fail address

IBIST start address

IBIST Address Register

1

IBIST fail address

IBIST peek/poke address

IBIST General Register

0

IBIST fail data

IBIST seed data

IBIST General Register

1

IBIST peek data

IBIST poke data

Table 10.2. Data BIST Address and General Registers

BIST Register

DBIST pause

Read

Write

DBIST Address Register

0

DBIST fail address

DBIST start address

DBIST Address Register

1

DBIST fail address

DBIST peek/poke address

DBIST General Register

0

DBIST fail data

DBIST seed data

DBIST General Register

1

DBIST peek data

DBIST poke data

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