10.3. BIST of memory arrays

Caution

Code for running the BIST must not be placed in the Instruction TCM or in a cacheable location, because this can cause invalid or dirty data to be introduced into program execution. Also, caches must be flushed after running the BIST.

Adding a simple memory test controller enables you to perform an exhaustive test of the memory arrays. You can activate BIST operation using an MCR to the CP15 BIST Control Register.

When you perform a BIST operation on compiled RAM, the functional enable for all RAMs is automatically disabled, forcing all memory accesses to all TCM and cache address ranges to go to the AHB. This enables you to run BIST operations in the background (for instance the Instruction TCM can be have BIST applied, while code is executed over the AHB).

Serial scan access to the CP15 BIST operations is also provided for production test purposes, using a special mode of operation of the INTEST wrapper. See ARM946E-S INTEST wrapper.

You can also perform limited BIST in debug state by using scan chain 15 to access the CP15 BIST Control Register. This is not necessarily recommended as the BIST operation corrupts the contents of the TCM being tested.

You can achieve full programmer control over the BIST mechanism through five registers that are mapped to CP15 register 15 address space. For details of the MCR/MRC instructions used to access these registers, see Register 15, BIST Control Registers.

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