10.3.4. Pause modes

It is recommended that you use the following production test sequence for the compiled RAM:

  1. Test each RAM using a full test.

  2. Test the BIST hardware for each RAM.

To enable testing of the BIST hardware, it is necessary to deliberately corrupt data in the RAM. This can be done by the ATPG tool if it recognizes the RAM parameters. Alternatively a pause mechanism enables you to halt the BIST test, enabling you to corrupt data within the RAM. The sequence for this is:

  1. Use an MCR instruction to write the address for the location to be corrupted to the relevant BIST Address Register.

  2. Use an MCR instruction to write the corrupted data to the BIST General Register.

You can restart the test using an MCR instruction to the BIST Control Register and then check to see that the corrupted data causes the test to fail. You can read the address at which the BIST operation failed and data from the BIST Address and General Registers.

In addition to controlling the addressing within the address and general registers, the pause bit also controls the progression of the BIST algorithm as described in Auto pause.


It is recommended that you do not write application code that relies on the presence of the BIST pause mode. ARM Limited does not guarantee to support this feature in future versions of the ARM946E-S processor.

Auto pause

If you set the pause bit in the BIST control register before you activate the test, the test runs in auto pause mode, where the BIST operation pauses at a predetermined point in the BIST algorithm. The test pauses after the first pass through RAM.

You can poll the BIST Control Register to detect when a test has paused (the running flag is clear). You can then corrupt the data, as described in Pause modes, before you restart the BIST test.


Auto pause only operates after the first pass of the BIST operation.

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