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The process of serial test and debug is best explained in conjunction with the JTAG state machine. Figure 9.4 shows the state transitions that occur in the TAP controller, with the state names and their numbers. State numbers are output from the ARM946E-S processor on DBGTAPSM[3:0].
Figure 9.4. TAP controller state transitions[1]
| Copyright © 2001-2003, 2007 ARM Limited. All rights reserved. | ARM DDI 0201D |
| Non-Confidential | |
| PDF version | |
| Home > Debug Support > The JTAG state machine |