9.3. The JTAG state machine

The process of serial test and debug is best explained in conjunction with the JTAG state machine. Figure 9.4 shows the state transitions that occur in the TAP controller, with the state names and their numbers. State numbers are output from the ARM946E-S processor on DBGTAPSM[3:0].

Figure 9.4. TAP controller state transitions[1]

[1] From IEEE Std. 1149.1-2001. Copyright 2001 IEEE. All rights reserved.

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